CS4202-JQ 데이터 시트보기 (PDF) - Cirrus Logic

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CS4202-JQ

Audio Codec ’97 with Headphone Amplifier

Cirrus Logic 

CS4202

3.3 AC-Link Protocol Violation - Loss of

SYNC

The CS4202 is designed to handle SYNC protocol

violations. The following are situations where the

SYNC protocol has been violated:

• The SYNC signal is not sampled high for exact-

ly 16 BIT_CLK clock cycles at the start of an

audio frame.

• The SYNC signal is not sampled high on the

256th BIT_CLK clock period after the previous

SYNC assertion.

• The SYNC signal goes active high before the

256th BIT_CLK clock period after the previous

SYNC assertion.

Upon loss of synchronization with the controller,

the CS4202 will ‘clear’ the Codec Ready bit in the

serial data input frame until two valid frames are

detected. During this detection period, the CS4202

will ignore all register reads and writes and will

discontinue the transmission of PCM capture data.

In addition, if the LOSM bit in the Misc. Crystal

Control Register (Index 60h) is ‘set’ (default), the

CS4202 will mute all analog outputs. If the LOSM

bit is ‘clear’, the analog outputs will not be muted.

20

DS549PP1

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