CS98100
Symbol
taxch1
taxcl1
taxper
todbck
todbck
taoper
todlr2
todsd2
Description
Min
AUD_XCLK High Time (AUD_XCLK is Input/Output) 40
AUD_XCLK Low Time (AUD_XCLK is Input/Output) 40
AUD_XCLK period (Input/Output)
27
AUD_BCK delay from AUD_XCLK(output) active
edge
AUD_BCK delay from AUD_XCLK(input) active
edge
AUD_BCK period
216
AUD_LRCK delay from AUD_BCK active edge
-10
AUD_D[3:0] delay from AUD_BCK active edge
-10
Typ
50
50
Table 6. Digital Audio Out Characteristics
1.Values are guaranteed by design only
2.It is recommanded that the output data should be taken at the opposite edge of the AUD_BCK.
Max
10
21
10
10
Unit
%
%
ns
ns
ns
ns
ns
ns
AUD_XCLK(Input/Output)
AUD_BCK(Output)
t axper
t axcl
t axch
t odbck
t aoper
* AUD_BCK(Output)
t odlr
AUD_LRCK(Output)
AUD_DO[3:0] (Output)
t odsd
* Active clock edge is programmable. Timing is referenced from active edge.
Figure 9. Digital Audio Out Timing Diagram
14