CXA2096 데이터 시트보기 (PDF) - Sony Semiconductor

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CXA2096

Digital CCD Camera Head Amplifier

Sony Semiconductor 

CXA2096N

CDS (SH1, SH2, SH3):

The CCD signal from the CCD image sensor is input to PIN and DIN where correlated double sampling (CDS)

is performed by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled, held and output

by the SH2 output, and the signal level is sampled, held and output by the SH3 output. SH1 and SH2 are the

sample-and-hold circuits for the precharge level; SH3 is the sample-and-hold circuit for the signal level.

CDSCLP 1, 2:

CDSCLP1 and 2 stabilize the input signal DC level, clamp (CLPDM) the input signal during the idle transfer

interval for the purpose of eliminating the AGC input offset, and adjust the DC level ([∗1], [∗2]) of SH2 and SH3

in line with VREF. CDSCLP1 is the clamp circuit for the precharge level, and CDSCLP2 is the clamp circuit for

the signal level.

AGC:

AGC is the gain control amplifier for the camera signal.

The gain can be varied from –1 to +31dB by adjusting the AGCCONT voltage control VAGCCONT from 1.5 to

3.0V.

CAM SH:

CAM SH is the sample-and-hold circuit for synchronizing the data read-in timing for the external A/D. Sampling

is possible according to the approximately 10ns sampling pulse width input to XRS.

AGCCLP:

The basic black level is set ([∗3]) by clamping the AGC output waveform with the CLPOB clock during the OPB

interval. When PBLK is High and CLPOB is Low, the clamping circuit operates, adjusting the AGCCLP current

so that the DRVOUT potential equals the OFFSET potential (which is determined by the voltage applied to the

OFFSET pin), thus setting the AGCCLP potential. The AGCCLP capacitance is connected to the AGCCLP pin.

DC SHIFT:

This circuit functions when AGCCLP operates, following the AGCCLP potential and forcing a DC shift of the

AGC output waveform OPB interval to the basic black level. When AGCCLP is not operating, the basic black

level is maintained at its previous setting.

BLK SW:

The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not

fall below the basic black level and replacing the DC potential with VRB. ([∗4])

The signal is blanked when PBLK is Low.

OFFSET:

OFFSET controls the DRV output waveform black level offset.

The offset of the DRVOUT camera signals can be adjusted when a voltage is applied to OFFSET. ([∗5])

The voltage controlled by OFFSET is output as the DRV output DC offset via AGCCLP, DCSHIFT, CAMSH

and BLKSW.

When the OFFSET voltage is 1.5 to 3.0V, DRVOUT DC can vary in a linear fashion from VRB + 100mV to VRB.

In addition, when the OFFSET voltage is 0V, DRVOUT DC is preset to VRB + 35mV.

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