CY22801KSXC-XXX(2011) 데이터 시트보기 (PDF) - Cypress Semiconductor

부품명

상세내역

제조사

CY22801KSXC-XXX
(Rev.:2011)

Universal Programmable Clock Generator (UPCG)

Cypress Semiconductor 

Timing Definitions

Figure 6. Duty Cycle Definition; DC = t2/t1

t1

t2

CLK

50%

50%

Figure 8. Period Jitter Definition

t6

CLK

50%

Figure 10. Cycle to Cycle Jitter Definition (CCJ)

TCycle_i

TCycle_i+1

50%

CLK

tCCJ = TCycle_i - TCycle_i+1 (over 1000 Cycles)

Figure 12. Output Enable and Disable Timing

OUTPUT

ENABLE

VIL

CLK

VIH

High

Impedance

tOE1

tOE2

CY22801

Figure 7. Rise and Fall Time Definitions

t3

t4

80%

CLK

20%

Figure 9. Skew Definition

t5

CLKx

50%

CLKy

50%

Figure 11. Power-Down and Power-Up Timing

POWER

VIH

DOWN

VIL

tPU

CLK

High

Impedance

tPD

Document #: 001-15571 Rev. *E

Page 16 of 23

[+] Feedback

Share Link: