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7C1325B-100 데이터 시트보기 (PDF) - Cypress Semiconductor
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7C1325B-100
256K x 18 Synchronous 3.3V Cache RAM
Cypress Semiconductor
7C1325B-100 Datasheet PDF : 17 Pages
First
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Timing Diagrams
(continued)
ZZ Mode Timing
[17, 18]
CLK
ADSP
ADSC
CE
1
CE
2
CE
3
HIGH
LOW
HIGH
ZZ
I
CC
I/Os
t
ZZS
I
CC
(active)
Three-state
I
CCZZ
CY7C1325B
t
ZZREC
Notes:
17. Device must be deselected when entering ZZ mode. See Cycle Description Table for all possible signal conditions to deselect the device.
18. I/Os are in three-state when exiting ZZ sleep mode.
15
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