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CY7C1340G 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1340G
4-Mbit (128K x 32) Pipelined DCD Sync SRAM
Cypress Semiconductor
CY7C1340G Datasheet PDF : 16 Pages
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Switching Waveforms
Read Timing
[17]
tCYC
CY7C1340G
CLK
ADSP
ADSC
ADDRESS
GW, BWE,BW
[A:D]
CE
ADV
OE
Data Out (Q)
tCH tCL
tADS tADH
tADS tADH
tAS tAH
A1
A2
tWES tWEH
tCES tCEH
A3
Burst continued with
new base address
Deselect
cycle
tADVS tADVH
ADV suspends burst
t
CLZ
High-Z
tCO
tOEHZ
Q(A1)
tOEV
tCO
tOELZ
tDOH
Q(A2) Q(A2 + 1)
Single READ
tCHZ
Q(A2 + 2)
Q(A2 + 3)
BURST READ
Q(A2) Q(A2 + 1) Q(A3)
Burst wraps around
to its initial state
DON’T CARE
UNDEFINED
Note:
17. On this diagram, when CE is LOW: CE
1
is LOW, CE
2
is HIGH and CE
3
is LOW. When CE is HIGH: CE
1
is HIGH or CE
2
is LOW or CE
3
is HIGH.
Document #: 38-05522 Rev. *D
Page 11 of 16
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