IS61C632A-7PQ 데이터 시트보기 (PDF) - Integrated Silicon Solution
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IS61C632A-7PQ Datasheet PDF : 16 Pages
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IS61C632A
ISSI®
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
tKC
Cycle Time
tKH
Clock High Time
tKL
Clock Low Time
tKQ
Clock Access Time
tKQX(4) Clock High to Output Invalid
tKQLZ(4,5) Clock High to Output Low-Z
tKQHZ(4,5) Clock High to Output High-Z
tOEQ Output Enable to Output Valid
tOEQX(4) Output Disable to Output Invalid
tOELZ(4,5) Output Enable to Output Low-Z
tOEHZ(4,5) Output Disable to Output High-Z
tAS
Address Setup Time
tSS
Address Status Setup Time
tCES Chip Enable Setup Time
tAH
Address Hold Time
tSH
Address Status Hold Time
tCEH Chip Enable Hold Time
tZZS
ZZ Standby(1)
tZZREC ZZ Recovery(2)
tCFG
Configuration Setup(3)
-4
Min. Max.
8—
4—
4—
—4
1.5 —
0—
1.5 4
— 4.5
0—
0—
— 4.5
2.5 —
2.5 —
2.5 —
0.5 —
0.5 —
0.5 —
2—
2—
25 —
-5
Min. Max.
10 —
4—
4—
—5
1.5 —
0—
1.5 5
—5
0—
0—
— 4.8
2.5 —
2.5 —
2.5 —
0.5 —
0.5 —
0.5 —
2—
2—
35 —
-6
Min. Max.
12 —
4—
4—
—6
2—
0—
26
—6
0—
0—
—6
2.5 —
2.5 —
2.5 —
0.5 —
0.5 —
0.5 —
2—
2—
45 —
-7
Min. Max.
13 —
6—
6—
—7
2—
0—
26
—6
0—
0—
—6
2.5 —
2.5 —
2.5 —
0.5 —
0.5 —
0.5 —
2—
2—
52 —
-8
Min. Max. Unit
15 — ns
6 — ns
6 — ns
— 8 ns
2 — ns
0 — ns
2 6 ns
— 6 ns
0 — ns
0 — ns
— 6 ns
2.5 — ns
2.5 — ns
2.5 — ns
0.5 — ns
0.5 — ns
0.5 — ns
2 — cyc
2 — cyc
60 — ns
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.
3. Configuration signal MODE is static and must not change during normal operation.
4. Guaranteed but not 100% tested. This parameter is periodically sampled.
5. Tested with the load in Figure 2.
14
Integrated Silicon Solution, Inc.
SR001-1B
05/18/98
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