CY62256VLL-70ZI(2004) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY62256VLL-70ZI Datasheet PDF : 13 Pages
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CY62256V
Switching Characteristics Over the Operating Range[7]
CY62256V-70 CY62256V25-100
Parameter
Description
Min. Max. Min. Max.
Unit
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
Write Cycle[10, 11]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[8]
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[8]
CE HIGH to High-Z[8, 9]
CE LOW to Power-up
CE HIGH to Power-down
70
100
ns
70
100
ns
10
10
ns
70
100
ns
35
75
ns
5
5
ns
25
50
ns
10
10
ns
25
50
ns
0
0
ns
70
100
ns
tWC
Write Cycle Time
70
100
ns
tSCE
CE LOW to Write End
60
90
ns
tAW
Address Set-up to Write End
60
90
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
50
80
ns
tSD
Data Set-up to Write End
30
60
ns
tHD
tHZWE
tLZWE
Data Hold from Write End
WE LOW to High-Z[8, 9]
WE HIGH to Low-Z[8]
0
0
ns
25
50
ns
10
10
ns
Notes:
7. Test conditions assume signal transition time of 5 ns or less timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05057 Rev. *D
Page 6 of 13
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