LHF32KZ5 데이터 시트보기 (PDF) - Sharp Electronics

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LHF32KZ5

Flash Memory 32M (× 8 or ×16)

Sharp Electronics 

sharp

LHF32KZ5

14

4.1 Read Array Command

Upon initial device power-up and after exit from deep

power-down mode, the device defaults to read array

mode. This operation is also initiated by writing the

Read Array command. The device remains enabled

for reads until another command is written. Once the

internal WSM has started a block erase, bank erase,

(multi) word/byte write or block lock-bit configuration,

the device will not recognize the Read Array

command until the WSM completes its operation

unless the WSM is suspended via an Erase Suspend

and (Multi) Word/byte Write Suspend command. The

Read Array command functions independently of the

VPP voltage and RP# must be VIH.

4.2 Read Identifier Codes Command

The identifier code operation is initiated by writing the

Read Identifier Codes command. Following the

command write, read cycles from addresses shown in

Figure 4 retrieve the manufacturer, device, block lock

configuration and block erase status (see Table 5 for

identifier code values). To terminate the operation,

write another valid command. Like the Read Array

command, the Read Identifier Codes command

functions independently of the VPP voltage and RP#

must be VIH. Following the Read Identifier Codes

command, the following information can be read:

Table 5. Identifier Codes

Code

Address Data

Manufacture Code

00000

00001

B0

Device Code

Block Status Code

00002

00003

D0

X0004(1)

X0005(1)

•Block is Unlocked

•Block is Locked

•Last erase operation

completed successfully

DQ0=0

DQ0=1

DQ1=0

•Last erase operation did

not completed successfully

DQ1=1

•Reserved for Future Use

NOTE:

DQ2-7

1. X selects the specific block status code to be

read. See Figure 4 for the device identifier code

memory map.

4.3 Read Status Register Command

The status register may be read to determine when a

block erase, bank erase, (multi) word/byte write or

block lock-bit configuration is complete and whether

the operation completed successfully(see Table 14).

It may be read at any time by writing the Read Status

Register command. After writing this command, all

subsequent read operations output data from the

status register until another valid command is written.

The status register contents are latched on the falling

edge of OE# or BE#(Either BE0# or BE1L#, BE1H#),

whichever occurs. OE# or BE#(Either BE0# or BE1L#,

BE1H#) must toggle to VIH before further reads to

update the status register latch. The Read Status

Register command functions independently of the

VPP voltage. RP# must be VIH.

The extended status register may be read to

determine multi word/byte write availability(see Table

14.1). The extended status register may be read at

any time by writing the Multi Word/Byte Write

command. After writing this command, all subsequent

read operations output data from the extended status

register, until another valid command is written. Multi

Word/Byte Write command must be re-issued to

update the extended status register latch.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3 and SR.1 are

set to "1"s by the WSM and can only be reset by the

Clear Status Register command. These bits indicate

various failure conditions (see Table 14). By allowing

system software to reset these bits, several

operations (such as cumulatively erasing or locking

multiple blocks or writing several bytes in sequence)

may be performed. The status register may be polled

to determine if an error occurs during the sequence.

To clear the status register, the Clear Status Register

command (50H) is written. It functions independently

of the applied VPP Voltage. RP# must be VIH. This

command is not functional during block erase, bank

erase, (multi) word/byte write block lock-bit

configuration, block erase suspend or (multi)

word/byte write suspend modes.

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