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DAC3154 Datasheet PDF : 46 Pages
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DAC3154
DAC3164
SLAS960 – MAY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS
Typical values at T A = 25°C, full temperature range is T MIN = –40°C to T MAX = 85°C, DAC sample rate = 500MSPS, 50%
clock duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUT FS = 20mA (unless otherwise
noted).
PARAMETERS
TEST CONDITIONS
DAC3154
MIN TYP MAX
DAC3164
UNIT
MIN TYP MAX
CMOS DIGITAL INPUTS (RESETB, SDENB, SCLK, SDIO, TXENABLE)
VIH
High-level input voltage
0.6x
IOVDD
0.6x
IOVDD
V
VIL
Low-level input voltage
IOVDD = 3.3 V, 2.5 V
or 1.8 V
IIH
High-level input current
–40
IIL
Low-level input current
–40
DIGITAL OUTPUTS – CMOS INTERFACE (SDOUT, SDIO)
0.25×
IOVDD
40
-40
40
-40
0.25×
IOVDD
V
40 μA
40 μA
VOH
High-level output voltage
IOVDD = 3.3 V, 2.5 V, 0.85×
or 1.8 V
IOVDD
0.85×
IOVDD
V
VOL
Low-level output voltage
0.125×
IOVDD
0.125×
IOVDD
V
SERIAL PORT TIMING
ts(SENDB)
Setup time, SDENB to rising edge of
SCLK
20
20
ns
ts(SDIO)
th(SDIO)
t(SCLK)
t(SCLKH)
t(SCLKL)
td(DATA)
Setup time, SDIO to rising edge of SCLK
Hold time, SDIO from rising edge of SCLK
Period of SCLK
High time of SCLK
Low time of SCLK
Data output delay after falling edge of
SCLK
10
5
100
40
40
10
10
ns
5
ns
100
ns
40
ns
40
ns
10
ns
TRESET Minimum RESTB pulsewidth
LVDS INTERFACE (D[x..0]P/N, DA[x..0]P/N , DB[x..0]P/N , DA_CLKP/N, DB_CLKP/N, DATACLKP/N, SYNCP/N, ALIGNP/N)
VA,B+
Logic high differential input voltage
threshold
175
175
mV
VA,B–
Logic low differential input voltage
threshold
-175
–175 mV
VCOM
ZT
CL
Input Common Mode Range
Internal termination
LVDS input capacitance
1.0 1.2
2.0
85 110
135
2
1.0 1.2
85 110
2
2.0 V
135 Ω
pF
12
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