DS1481S/TR 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS1481S/TR

1–Wire Bus Master with Overdrive

Dallas Semiconductor -> Maxim Integrated 

DS1481

TIMING DIAGRAM: HOST INTERFACE Figure 4

ENI

D/CLK

RES

VALID

VALID

O1/BSY1

O2/BSY2

READ 0

(I/O)

READ 1

(I/O)

WRITE 1

(I/O)

tBLB

tSIO

tSIO = 8 µs (TYPICAL), tBLB = 60 µs (MINIMUM)

tSIO = 2 µs (MAXIMUM), tBLB = 6 µs (MINIMUM)

READ O, READ 1, WRITE 1 BIT TIME SLOTS

(OD = 0)

(OD = 1)

TIMING DIAGRAM: HOST INTERFACE Figure 5

ENI

D/CLK

RES

VALID

VALID

O1/BSY1

O2/BSY2

WRITE 0

(I/O)

tBLB

tBLB = 60 µs (MINIMUM)

tBLB = 6 µs (MINIMUM)

(OD = 0)

(OD = 1)

WRITE 0 TIME SLOT

021798 6/10

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