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DS2431 데이터 시트보기 (PDF) - Maxim Integrated

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DS2431
MaximIC
Maxim Integrated MaximIC
DS2431 Datasheet PDF : 26 Pages
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1024-Bit, 1-Wire EEPROM
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
MASTER Tx "RESET PULSE"
tRSTL
tF
RESISTOR
MASTER Rx "PRESENCE PULSE"
ε
tMSP
tPDH
MASTER
tPDL
tRSTH
tREC
DS2431
Figure 10. Initialization Procedure: Reset and Presence Pulse
Read/Write Time Slots
Data communication with the DS2431 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time
slots transfer data from slave to master. Figure 11 illus-
trates the definitions of the write and read time slots.
All communication begins with the master pulling the
data line low. As the voltage on the 1-Wire line falls
below the threshold VTL, the DS2431 starts its internal
timing generator that determines when the data line is
sampled during a write time slot and how long data is
valid during a read time slot.
Master-to-Slave
For a write-one time slot, the voltage on the data line
must have crossed the VTH threshold before the write-
one low time tW1LMAX is expired. For a write-zero time
slot, the voltage on the data line must stay below the
VTH threshold until the write-zero low time tW0LMIN is
expired. For the most reliable communication, the volt-
age on the data line should not exceed VILMAX during
the entire tW0L or tW1L window. After the VTH threshold
has been crossed, the DS2431 needs a recovery time
tREC before it is ready for the next time slot.
Slave-to-Master
A read-data time slot begins like a write-one time slot.
The voltage on the data line must remain below VTL
until the read low time tRL is expired. During the tRL
window, when responding with a 0, the DS2431 starts
pulling the data line low; its internal timing generator
determines when this pulldown ends and the voltage
starts rising again. When responding with a 1, the
DS2431 does not hold the data line low at all, and the
voltage starts rising as soon as tRL is over.
The sum of tRL + δ (rise time) on one side and the inter-
nal timing generator of the DS2431 on the other side
define the master sampling window (tMSRMIN to
tMSRMAX), in which the master must perform a read
from the data line. For the most reliable communication,
tRL should be as short as permissible, and the master
should read close to but no later than tMSRMAX. After
reading from the data line, the master must wait until
tSLOT is expired. This guarantees sufficient recovery
time tREC for the DS2431 to get ready for the next time
slot. Note that tREC specified herein applies only to a
single DS2431 attached to a 1-Wire line. For multide-
vice configurations, tREC must be extended to accom-
modate the additional 1-Wire device input capacitance.
Alternatively, an interface that performs active pullup
during the 1-Wire recovery time such as the DS2482-
x00 or DS2480B 1-Wire line drivers can be used.
______________________________________________________________________________________ 17

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