DSP56303 데이터 시트보기 (PDF) - Freescale Semiconductor

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DSP56303

DSP56303 24-bit digital signal processor (DSP)

Freescale Semiconductor 

DSP56303 Overview

PCU features include the following:

„ Position-independent code support

„ Addressing modes optimized for DSP applications (including immediate offsets)

„ Instruction cache controller

„ Internal memory-expandable hardware stack

„ Nested hardware DO loops

„ Fast auto-return interrupts

„ Hardware system stack

The PCU uses the following registers:

„ Program counter register

„ Status register

„ Loop address register

„ Loop counter register

„ Vector base address register

„ Size register

„ Stack pointer

„ Operating mode register

„ Stack counter register

1.6.4 PLL and Clock Oscillator

The clock generator in the DSP56300 core comprises two main blocks: the PLL, which performs

clock input division, frequency multiplication, and skew elimination; and the clock generator,

which performs low-power division and clock pulse generation. These features allow you to:

„ Change the low-power divide factor without losing the lock

„ Output a clock with skew elimination

The PLL allows the processor to operate at a high internal clock frequency using a low-frequency

clock input, a feature that offers two immediate benefits:

„ A lower-frequency clock input reduces the overall electromagnetic interference generated

by a system.

„ The ability to oscillate at different frequencies reduces costs by eliminating the need to

add additional oscillators to a system.

DSP56303 User’s Manual, Rev. 2

1-8

Freescale Semiconductor

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