DSP56303 데이터 시트보기 (PDF) - Freescale Semiconductor
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DSP56303 Datasheet PDF : 292 Pages
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2.1 Power
Power
Table 2-2. Power Inputs
Power Name
Description
VCCP
PLL Power
VCC dedicated for use with Phase Lock Loop (PLL). The voltage should be well-regulated and the input
should be provided with an extremely low impedance path to the VCC power rail.
VCCQ (4)
Quiet Power
An isolated power for the internal processing logic. This input must be tied externally to all other chip
power inputs, except for VCCP. The user must provide adequate external decoupling capacitors.
VCCA (4)
Address Bus Power
An isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other
chip power inputs, except for VCCP. The user must provide adequate external decoupling capacitors.
VCCD (4)
Data Bus Power
An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other
chip power inputs, except for VCCP. The user must provide adequate external decoupling capacitors.
VCCC (2)
Bus Control Power
An isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power
inputs, except for VCCP. The user must provide adequate external decoupling capacitors.
VCCH
Host Power
An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power inputs,
except for VCCP. The user must provide adequate external decoupling capacitors.
VCCS (2)
ESSI, SCI, and Timer Power
An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other
chip power inputs, except for VCCP. The user must provide adequate external decoupling capacitors.
Note:
These designations are package-dependent. Some packages connect all VCC inputs except VCCP to each other
internally. On those packages, all power input except VCCP are labeled VCC. The numbers of connections indicated
in this table are minimum values; the total VCC connections are package-dependent.
2.2 Ground
Table 2-3. Grounds
Ground Name
GNDP
GNDP1
GNDQ (4)
Description
PLL Ground
Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground. VCCP should be bypassed to GNDP by a 0.47 µF capacitor located as close as possible
to the chip package.
PLL Ground 1
Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground.
Quiet Ground
An isolated ground for the internal processing logic. This connection must be tied externally to all other
chip ground connections, except GNDP and GNDP1. The user must provide adequate external
decoupling capacitors.
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor
2-3
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