DSP56300FM 데이터 시트보기 (PDF) - Freescale Semiconductor
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DSP56300FM Datasheet PDF : 148 Pages
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External Memory Expansion Port (Port A)
Table 3-8 SRAM Read and Write Accesses1 (continued)
No.
Characteristics
Symbol
Expression2
Min Max Unit
118 TA setup before RD or WR deassertion4
0.25 × TC + 2.0
4.5
—
ns
119 TA hold after RD or WR deassertion
0
—
ns
1 All timings for 100 MHz are measured from 0.5 · Vcc to .05 · Vcc
2 WS is the number of wait states specified in the BCR.
3 Timings 100, 107 are guaranteed by design, not tested.
4 In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active.
A0–A17
AA0–AA1
RD
WR
TA
D0–D7
100
113
116
117
115
105
106
104
119
118
Data
In
Figure 3-9 SRAM Read Access
AA0468
Freescale Semiconductor
DSP56364 Technical Data, Rev. 4.1
3-15
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