E28F004BL-T150 데이터 시트보기 (PDF) - Intel

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E28F004BL-T150

4-MBlT (256K x 16, 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY

Intel 

28F400BL-T B 28F004BL-T B

Similar to erasure the status register indicates

whether programming is complete While the pro-

gram sequence is executing bit 7 of the status regis-

ter is a ‘‘0’’ The status register can be polled by

toggling either CE or OE to determine when the

program sequence is complete Only the Read

Status Register command is valid while program-

ming is active

When programming is complete the status bits

which indicate whether the program operation was

successful should be checked If the programming

operation was unsuccessful Bit 4 of the status regis-

ter is set to a ‘‘1’’ to indicate a Program Failure If

Bit 3 is set then VPP was not within acceptable limits

and the WSM will not execute the programming se-

quence

The status register should be cleared before at-

tempting the next operation Any CUI instruction can

follow after programming is completed however it

must be recognized that reads from the memory

status register or Intelligent Identifier cannot be ac-

complished until the CUI is given the appropriate

command A Read Array command must first be giv-

en before memory contents can be read

Figure 12 shows a system software flowchart for de-

vice byte programming operation Figure 13 shows a

similar flowchart for device word programming oper-

ation (28F400BL-only)

4 4 5 ERASE MODE

Erasure of a single block is initiated by writing the

Erase Setup and Erase Confirm commands to the

CUI along with the addresses A 12 17 for the

28F400BL or A 12 18 for the 28F004BL identifying

the block to be erased These addresses are latched

internally when the Erase Confirm command is is-

sued Block erasure results in all bits within the block

being set to ‘‘1’’

The WSM will execute a sequence of internally

timed events to

1 program all bits within the block

2 verify that all bits within the block are sufficiently

programmed

3 erase all bits within the block and

4 verify that all bits within the block are sufficiently

erased

While the erase sequence is executing Bit 7 of the

status register is a ‘‘0’’

When the status register indicates that erasure is

complete the status bits which indicate whether the

erase operation was successful should be checked

If the erasure operation was unsuccessful Bit 5 of

the status register is set to a ‘‘1’’ to indicate an

Erase Failure If VPP was not within acceptable limits

after the Erase Confirm command is issued the

WSM will not execute an erase sequence instead

Bit 5 of the status register is set to a ‘‘1’’ to indicate

an Erase Failure and Bit 3 is set to a ‘‘1’’ to identify

that VPP supply voltage was not within acceptable

limits

The status register should be cleared before at-

tempting the next operation Any CUI instruction can

follow after erasure is completed however it must

be recognized that reads from the memory array

status register or Intelligent Identifier can not be ac-

complished until the CUI is given the appropriate

command A Read Array command must first be giv-

en before memory contents can be read

Figure 13 shows a system software flowchart for

Block Erase operation

4 4 5 1 Suspending and Resuming Erase

Since an erase operation typically requires 2 sec-

onds to 5 seconds to complete an Erase Suspend

command is provided This allows erase-sequence

interruption in order to read data from another block

of the memory Once the erase sequence is started

writing the Erase Suspend command to the CUI re-

quests that the Write State Machine (WSM) pause

the erase sequence at a predetermined point in the

erase algorithm The status register must be read to

determine when the erase operation has been sus-

pended

At this point a Read Array command can be written

to the CUI in order to read data from blocks other

than that which is being suspended The only other

valid command at this time is the Erase Resume

command or Read Status Register operation

Figure 14 shows a system software flowchart detail-

ing the operation

During Erase Suspend mode the chip can go into a

pseudo-standby mode by taking CE to VIH and the

active current is now a maximum of 6 mA If the chip

is enabled while in this mode by taking CE to VIL

the Erase Resume command can be issued to re-

sume the erase operation

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