EL2157CN 데이터 시트보기 (PDF) - Elantec -> Intersil
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EL2157CN Datasheet PDF : 20 Pages
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EL2150C EL2157C
125 MHz Single Supply Clamping Op Amps
Applications Information Contd
As far as the output stage of the amplifier is con-
cerned RFa RG appear in parallel with RL for
gains other than a1 As this combination gets
smaller the bandwidth falls off Consequently
RF has a minimum value that should not be ex-
ceeded for optimum performance
For AV e a1 RF e 0X is optimum For Av e
b1 or a2 (noise gain of 2) optimum response is
obtained with RF between 500X and 1 kX For
Av e b4 or a5 (noise gain of 5) keep RF be-
tween 2 kX and 10 kX
Video Performance
For good video performance an amplifier is re-
quired to maintain the same output impedance
and the same frequency response as DC levels are
changed at the output This can be difficult when
driving a standard video load of 150X because of
the change in output current with DC level Dif-
ferential Gain and Differential Phase for the
EL2150C EL2157C are specified with the black
level of the output video signal set to a1 2V
This allows ample room for the sync pulse even
in a gain of a2 configuration This results in dG
and dP specifications of 0 05% and 0 05 while
driving 150X at a gain of a2 Setting the black
level to other values although acceptable will
compromise peak performance For example
looking at the single supply dG and dP curves for
RLe150 X if the output black level clamp is re-
duced from 1 2V to 0 6V dG dP will increase
from 0 05% 0 05 to 0 08% 0 25 Note that in a
gain of a2 configuration this is the lowest black
level allowed such that the sync tip doesn’t go
below 0V
If your application requires that the output goes
to ground then the output stage of the
EL2150C EL2157C like all other single supply
op amps requires an external pull down resistor
tied to ground As mentioned above the current
flowing through this resistor becomes the DC
bias current for the output stage NPN transistor
As this current approaches zero the NPN turns
off and dG and dP will increase This becomes
more critical as the load resistor is increased in
value While driving a light load such as 1 kX if
the input black level is kept above 1 25V dG and
dP are a respectable 0 03% and 0 03
For other biasing conditions see the Differential
Gain and Differential Phase vs Input Voltage
curves
Output Drive Capability
In spite of their moderately low 5 mA of supply
current the EL2150C EL2157C are capable of
providing g100 mA of output current into a 10X
load or g60 mA into 50X With this large output
current capability a 50X load can be driven to
g3V with VS e g5V making it an excellent
choice for driving isolation transformers in tele-
communications applications
Driving Cables and Capacitive Loads
When used as a cable driver double termination
is always recommended for reflection-free per-
formance For those applications the back-termi-
nation series resistor will de-couple the
EL2150C EL2157C from the cable and allow ex-
tensive capacitive drive However other applica-
tions may have high capacitive loads without a
back-termination resistor In these applications a
small series resistor (usually between 5X and
50X) can be placed in series with the output to
eliminate most peaking The gain resistor (RG)
can then be chosen to make up for any gain loss
which may be created by this additional resistor
at the output
Disable Power-Down
The EL2157C amplifier can be disabled placing
its output in a high-impedance state The disable
or enable action takes only about 40 nsec When
disabled the amplifier’s supply current is re-
duced to 0 mA thereby eliminating all power
consumption by the EL2157C The EL2157C am-
plifier’s power down can be controlled by stan-
dard CMOS signal levels at the ENABLE pin
The applied CMOS signal is relative to the GND
pin For example if a single a5V supply is used
the logic voltage levels will be a0 5V and a2 0V
If using dual g5V supplies the logic levels will
be b4 5V and b3 0V Letting the ENABLE pin
float will disable the EL2157C If the power-
down feature is not desired connect the EN-
ABLE pin to the VSa pin The guaranteed logic
levels of a0 5V and a2 0V are not standard TTL
levels of a0 8V and a2 0V so care must be tak-
en if standard TTL will be used to drive the EN-
ABLE pin
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