4581CS(2008) 데이터 시트보기 (PDF) - Intersil
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4581CS Datasheet PDF : 10 Pages
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EL4581
fixed level above the clamp voltage VR1. The output of C2
initiates the timing one-shots for gating the sample and hold
circuits. The sample of the sync tip is delayed by 0.8µs to
enable the actual sample of 2µs to be taken on the optimum
section of the sync. pulse tip. The acquisition time of the
circuit is about three horizontal lines. The double poly CMOS
technology enables long time constants to be achieved with
small high quality on-chip capacitors. The back porch
voltage is similarly derived from the trailing edge of sync,
which also serves to cut off the tip sample if the gate time
exceeds the tip period. Note that the sample and hold gating
times will track RSET through IOT.
The 50% level of the sync tip is derived, through the resistor
divider R1 and R2, from the sample and held voltages VTIP
and VBP, and applied to the plus input of comparator C1.
This comparator has built in hysteresis to avoid false
triggering. The output of C2 is a digital 5V signal which feeds
the C/S output buffer B1 and the other internal circuit blocks,
the vertical, back porch and odd/even functions.
The vertical circuit senses the C/S edges and initiates an
integrator which is reset by the shorter horizontal sync
pulses but times out the longer vertical sync. pulse widths.
Block Diagram
The internal timing circuits are referenced to IOT and VR3,
the time-out period being inversely proportional to the timing
current. The vertical output pulse is started on the first
serration pulse in the vertical interval and is then self-timed
out. In the absence of a serration pulse, an internal timer will
default the start of vertical.
The back porch is triggered from the sync tip trailing edge
and initiates a one-shot pulse. The period of this pulse is
again a function of IOT and will therefore track the scan rate
set by RSET.
The odd/even circuit (O/E) comprises of flip flops which track
the relationship of the horizontal pulses to the leading edge
of the vertical output, and will switch on every field at the
start of vertical. Pin 7 is high during the odd field.
Loss of video signal can be detected by monitoring the C/S
output. The 50% level of the previous video signal will
remain held on the S/H capacitors after the input video
signal has gone and the input on pin 2 has defaulted to the
clamp voltage. Consequently, the C/S output will remain low
longer than the normal vertical pulse period. An external
timing circuit could be used to detect this condition.
1
B1
C SYNC OUT
CS
VDD
8
VDD
VR1
A1
CLAMP
VIDEO IN
2
C1
I1
3-POLE FILTER
-
F1
+C1
IOT
VBP
S/H
R1
C2
VR2
R2
IOT
VTIP
VERTICAL
OUT
3
D2
GND
4
VERTICAL
VR1
DETECT
VR2
IOT VR3
VR3
O/E
DETECT
ODD/EVEN
OUT
B4
7
IREF ITR
IOT
VR4 +
VREF
-A2
Q1
R3RSET
6
BACK
PORCH
DETECT
IOT VR3
RSET
*NOTE:
RSET MUST BE A
1% RESISTOR.
B3
5
BURST/BACK
PORCH OUT
FIGURE 14. STANDARD (NTSC INPUT) H. SYNC DETAIL
8
FN7172.1
February 8, 2008
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