EL5120 데이터 시트보기 (PDF) - Intersil
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EL5120 Datasheet PDF : 12 Pages
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EL5120, EL5220, EL5420
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
3
2.500W
2.5
QFN16
θJA=40°C/W
2
TSSOP14
1.5
θJA=100°C/W
1.136W
SO14
1
1.0W
θJA=88°C/W
870mW
0.5
MSOP8
θJA=115°C/W
0
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 27. PACKAGE POWER DISSIPATION VS AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
0.9 833mW
0.8
0.7 667mW
SO14
θJA=120°C/W
0.6
606mW
0.5
0.4 486mW
QFN16
θJA=150°C/W
0.3
MSOP8
0.2
θJA=206°C/W
0.1
TSSOP14
θJA=165°C/W
0
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 28. PACKAGE POWER DISSIPATION VS AMBIENT
TEMPERATURE
Unused Amplifiers
It is recommended that any unused amplifiers in a dual and
a quad package be configured as a unity gain follower. The
inverting input should be directly connected to the output
and the non-inverting input tied to the ground plane.
Driving Capacitive Loads
The EL5120, EL5220, and EL5420 can drive a wide range of
capacitive loads. As load capacitance increases, however,
the -3dB bandwidth of the device will decrease and the
peaking increase. The amplifiers drive 10pF loads in parallel
with 10kΩ with just 1.5dB of peaking, and 100pF with 6.4dB
of peaking. If less peaking is desired in these applications, a
small series resistor (usually between 5Ω and 50Ω) can be
placed in series with the output. However, this will obviously
reduce the gain slightly. Another method of reducing peaking
is to add a “snubber” circuit at the output. A snubber is a
shunt load consisting of a resistor in series with a capacitor.
Values of 150Ω and 10nF are typical. The advantage of a
snubber is that it does not draw any DC load current or
reduce the gain
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5120, EL5220, and EL5420 can provide gain at high
frequency. As with any high-frequency device, good printed
circuit board layout is necessary for optimum performance.
Ground plane construction is highly recommended, lead
lengths should be as short as possible and the power supply
pins must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the VS- pin is
connected to ground, a 0.1µF ceramic capacitor should be
placed from VS+ to pin to VS- pin. A 4.7µF tantalum
capacitor should then be connected in parallel, placed in the
region of the amplifier. One 4.7µF capacitor may be used for
multiple devices. This same capacitor combination should be
placed at each supply pin to ground if split supplies are to be
used.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN7186.4
February 21, 2005
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