EL5421T 데이터 시트보기 (PDF) - Intersil

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EL5421T

12MHz Rail-to-Rail Input-Output Buffer

Intersil 

EL5421T

Typical Performance Curves (Continued)

VOUTA

CLA

RLA

EL5421T

(10LD MSOP shown)

1 VOUTA

VOUTD 10

VOUTD

RLD

CLD

VINA+

49.9

VS+

+

4.7µF

VINB+

49.9

2 VINA

3 Vs+

0.1µF

4 VINB

VIND 9

VIND+

49.9

Vs- 8

0.1µF

VS-

+ 4.7µF

VINC 7

VINC+

49.9

VOUTB

CLB

5 VOUTB

VOUTC 6

RLB

RLC

FIGURE 24. BASIC TEST CIRCUIT

VOUTC

CLC

Pin Descriptions

PIN NUMBER

1

2

3

4

5

PIN NAME

VOUTA

VINA

VS+

VINB

VOUTB

6

VOUTC

7

VINC

8

VS-

9

VIND

10

VOUTD

FUNCTION

Buffer A Output

Buffer A Input

Positive Power Supply

Buffer B Input

Buffer B Output

Buffer C Output

Buffer C Input

Negative Power Supply

Buffer D Input

Buffer D Output

EQUIVALENT CIRCUIT

(Reference Circuit 1)

(Reference Circuit 2)

(Reference Circuit 2)

(Reference Circuit 1)

(Reference Circuit 1)

(Reference Circuit 2)

(Reference Circuit 1)

(Reference Circuit 2)

VS+

VOUTx

VS-

GND

CIRCUIT 1

VINx

VS+

VS-

CIRCUIT 2

9

FN6922.0

September 25, 2009

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