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EN5312Q

Fully Integrated Voltage Mode Synchronous Buck PWM DC-DC Converter Module

Unspecified 

Rev. 0.87 – January 2006

EN5312Q

PARAMETER

SYMBOL

TEST CONDITIONS

MIN TYP MAX UNITS

Hysteresis

Voltage Accuracy

All parts over line, load and

Temp

±2

%

Voltage Regulation

Any given part, Over load, line,

temp

±1

%

Soft-Start Operation

Time to 90% Vout

Tss Vout = 3.3V

1.6

mSec

Pin Description

VIN

1

VIN

2

GND 3

GND 4

VOUT 5

VOUT 6

EN5312Q

16 VFB

15 VSENSE

14 NC

13 NC

12 NC

11 NC

VFB 16

VSENSE 15

NC 14

NC 13

NC 12

NC 11

AGND

EN5312Q

1 VIN

2 VIN

3 GND

4 GND

5 VOUT

6 VOUT

Figure 2. Pin description, top view.

Figure 3. Pin description, bottom view.

VIN (Pin 1,2): Input voltage pin. Supplies power to

the IC. VIN can range from 2.4V to 5.5V.

the best regulation. When using external divider,

connect this pin to VOUT.

GND: (Pin 3,4): Power ground. This pin is

internally connected to bottom thermal/ground pad

(AGND). Input and output filter capacitors should

be connected to this pin. Good EMI design practice

dictates that these pins not be connected to other

ground connections. The large thermal pad on the

bottom of the package should be the single point of

contact to system ground. (refer to section on EMI

layout consideration for more detail).

VOUT (Pin 5,6,7): Regulated output voltage.

NC (Pin 8,9,10,11,12,13,14): These pins should not

be electrically connected to each other or to any

external signal, voltage, or ground. One or more of

these pins may be connected internally.

VSENSE (Pin 15): Sense pin for preset output

voltages. When using preset voltages connect this

to VLOAD or as close to VLOAD as possible to ensure

VFB (Pin 16): Feed back pin for external divider

option. When using the external divider option

(VS0=VS1=VS2= high) connect this pin to the

center of the external divider. Set the divider such

that VFB = 0.6V.

VS0,VS1,VS2 (Pin 17,18,19): Output voltage

select. VS0=pin19, VS1=pin18, VS2=pin17.

Selects one of seven preset output voltages or

choose external divider by connecting pins to logic

high or low. Logic low is defined as VLOW ≤ 0.4V.

Logic high is defined as VHIGH ≥ 1.4V. Any level

between these two values is indeterminate. (refer to

section on output voltage select for more detail).

ENABLE (Pin 20): Output enable. Enable = logic

high, disable = logic low. Logic low is defined as

VLOW ≤ 0.4V. Logic high is defined as VHIGH ≥

Rev. 0.87 – January 2006

3

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