CF52005-3.0 데이터 시트보기 (PDF) - Altera Corporation

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CF52005-3.0

Configuration Devices for SRAM-Based LUT Devices

Altera Corporation 

Timing Information

Page 17

Table 9 lists the timing parameters when using EPC1 and EPC1441 devices at 3.3 V.

Table 9. Timing Parameters when Using EPC1 and EPC1441 Devices at 3.3 V

Symbol

Parameter

Min

Typ

Max Units

tPO R

tOEZX

tCE

tDSU

tDH

tCO

tCD OE

fCLK

tMCH

tMCL

tSCH

tSCL

tCASC

tCCA

tOEW

tOEC

tNRCAS

POR delay (1)

OE high to DATA output enabled

OE high to first rising edge on DCLK

Data setup time before rising edge on DCLK

Data hold time after rising edge on DCLK

DCLK to DATA out

DCLK to DATA enable/disable

DCLK frequency

DCLK high time for the first device in the configuration chain

DCLK low time for the first device in the configuration chain

DCLK high time for subsequent devices

DCLK low time for subsequent devices

DCLK rising edge to nCASC

nCS to nCASC cascade delay

OE low pulse width (reset) to guarantee counter reset

OE low (reset) to DCLK disable delay

OE low (reset) to nCASC delay

—

—

200

ms

—

—

80

ns

—

—

300

ns

30

—

—

ns

0

—

—

ns

—

—

30

ns

—

—

30

ns

2

4

10

MHz

50

125

250

ns

50

125

250

ns

50

—

—

ns

50

—

—

ns

—

—

25

ns

—

—

15

ns

100

—

—

ns

—

—

30

ns

—

—

30

ns

Note to Table 9:

(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.

Table 10 lists the timing parameters when using EPC1, EPC2, and EPC1441 devices at

5.0 V.

Table 10. Timing Parameters when Using EPC1, EPC2, and EPC1441 Devices at 5.0 V (Part 1 of 2)

Symbol

tPO R

tOEZX

tCE

tDSU

tDH

tCO

tCD OE

fCLK

tMCH

tMCL

tSCH

tSCL

tCASC

tCCA

Parameter

POR delay (1)

OE high to DATA output enabled

OE high to first rising edge on DCLK

Data setup time before rising edge on DCLK

Data hold time after rising edge on DCLK

DCLK to DATA out

DCLK to DATA enable/disable

DCLK frequency

DCLK high time for the first device in the configuration chain

DCLK low time for the first device in the configuration chain

DCLK high time for subsequent devices

DCLK low time for subsequent devices

DCLK rising edge to nCASC

nCS to nCASC cascade delay

Min

Typ

—

—

—

—

—

—

30

—

0

—

—

—

—

—

6.7

10

30

50

30

50

30

—

30

—

—

—

—

—

Max Units

200

ms

50

ns

200

ns

—

ns

—

ns

20

ns

20

ns

16.7 MHz

75

ns

75

ns

—

ns

—

ns

20

ns

10

ns

January 2012 Altera Corporation

Configuration Devices for SRAM-Based LUT Devices

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