FA5528 데이터 시트보기 (PDF) - Fuji Electric
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FA5528 Datasheet PDF : 33 Pages
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FA5526/5527/5528/5536/5537/5538
(5) Minimum ON pulse width
As described in “(4) Blanking,” the input voltage at the
IS pin is ignored during a blanking period right after
turn-on. Consequently, the sum of blanking time and
output delay time (100ns) is the minimum ON pulse
width at the OUT pin of the IC. The minimum ON pulse
width for FA5526/36, FA5527/37 and FA5528/38 are
300ns, 500ns and 700ns, respectively.
In addition, a dedicated comparator is incorporated not
to generate pulses at no load.
When FB pin voltage is below 0.28V or CS pin voltage
is below 0.68V, the output of the comparator is inverted
and a clear signal “CLR” is input to the blanking circuit.
Then, the blanking circuit will not output a set signal and
no set signals will be input to PMW latch (F.F.), keeping
the output voltage low.
(See “9-(14) Timing chart.”)
(6) Slope compensation
5V Reg.
In the current mode control, subharmonic oscillation
may occur at a continuous current mode operation with
a duty cycle of 50% or more.
To avoid this, FA5526/36, FA5527/37 and FA5528/38
have built-in slope compensation circuits.
FB
2
7.4k
1Meg
5pF
OSC
VCO Q
For details of subharmonic oscillation phenomenon
and slope compensation effect, see p.32.
As shown in Fig.9, slope compensation is achieved by
SLOPE
( CS pin voltage ) / 4
GENERATOR
60k
Ramp Signal
20k
+-Σ
IS comp.
0.52V
a input of FB pin voltage to the current comparator (IS
comp.), which subtracted ramp signal generated from
3
Rs
IS
oscillator passing through slope generator.
Fig.9 Slope compensation circuit
Therefore, the threshold voltage at the FB pin
gradually decreases with time within each switching
cycle as shown in Fig.10 even when voltages at the FB
pin and CS pin are constant.
(See “9-(14) Timing chart.”)
Fuji Electric Co., Ltd.
AN-087E Rev.1.0
April-2011
Fig.10 Slope compensation
18
http://www.fujielectric.co.jp/products/semiconductor/
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