FA5591N 데이터 시트보기 (PDF) - Fuji Electric

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FA5591N

Power Supply Control IC(Power Factor Correction)

Fuji Electric 

FA5590N,FA5591N

11. Description of use for each pin

(1) Terminal No. 1 (FB terminal)

Functions

(i) Input of feedback signal of output voltage setting

(ii) Detect short-circuit of FB terminal

(iii) Detect output overvoltage

Application

(i) Feedback signal input

- Wiring

Connect the node between voltage dividing resistors for setting output

voltage.

- Operation

The output voltage Vout of PFC is controlled so that FB voltage matches

the internal reference voltage (2.5V).

To detect FB terminal opening, pull-up current (Ipullup) is supplied to the

FB terminal. This current flows to GND via R2. For this reason,

resistance R1, R2 should be set in consideration of this current when the

output voltage (Vout) is set.

Vout  (VREF / R2  Ipullup)  R1  VREF

VREF : Reference voltage =2.5V(typ)

Ipullup : FB terminal pull-up current =1.8uA(typ)

To prevent malfunction due to noise, capacitor C3 of 100pF~3300pF

should be connected between the FB terminal and GND.

(ii) FB terminal short-circuit detection

- Wiring

Same as for the (i) Feedback signal input

- Operation

When the input voltage of the FB terminal becomes 0.3V or lower due to

short-circuit of R2, the output of the comparator (SP) inverts to stop the

output of the IC.

(iii) Output overvoltage detection

- Wiring

Same as for the (i) Feedback signal input

- Operation

Normally the voltage of the FB terminal is 2.5V almost same as the

reference voltage of the error amplifier. When the output voltage rises for

some reason and the voltage of the FB terminal reaches the comparator

reference voltage (1.09*VREF), the output of the comparator (OVP)

inverts to stop the OUT pulse. If the output voltage returns to the normal

value, the OUT pulse resumes.

(2) Terminal No. 2 (COMP terminal)

Function

(i) Phase compensation of internal ERRAMP output

Application

(i) Phase compensation of internal ERRAMP output

- Wiring

Connect C, R between COMP terminal and GND as shown in Fig. 16.

- Operation

Connecting C, R to the COMP terminal suppress ripple component at 2

times the frequency of the AC line that appears in the FB output.

Vout

1.8uA

VREF(2.5V)

R1

FB

1

COMP

R2

C3

ERRAMP

Short Ｃｏｍｐ

SP

Vthfb(0.3V)

Vsovp(1.09*VREF)

OVP

ＯＶＰ Ｃｏｍｐ

Vdovp(1.05*VREF)

RAMP OSC

Ｄｙｎａｍｉｃ ＯＶＰ

Fig.15 FB pin circuit

PWM.comp COMP

2

ERRAMP

R3

C4

C5

Fig.16 COMP pin circuit

Fuji Electric Co., Ltd.

AN-016E Rev.1.2

April-2011

16

http://www.fujielectric.co.jp/products/semiconductor/

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