AS4SD4M16(2001) 데이터 시트보기 (PDF) - Austin Semiconductor

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AS4SD4M16
(Rev.:2001)

4 Meg x 16 SDRAM Synchronous DRAM Memory

Austin Semiconductor 

Austin Semiconductor, Inc.

SDRAM

AS4SD4M16

4 Meg x 16 SDRAM

Synchronous DRAM Memory

FEATURES

• Extended Testing Over -55°C to +125° C and

Industrial Temp -40°C to 85° C

• WRITE Recovery ( tWR/ tDPL) tWR = 2 CLK

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal pipelined operation; column address can be

changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8 or full page

• Auto Precharge and Auto Refresh Modes

• Self Refresh Mode (Industrial, -40°C to 85° C only)

• 4,096-cycle refresh

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

• Longer lead TSOP for improved reliability

(OCPL*)

• Short Flow / Long Flow Test Screening Options

OPTIONS

MARKING

• Configurations

4 Meg x 16 (1 Meg x 16 x 4 banks)

4M16

• Plastic Package - OCPL*

54-pin TSOP (400 mil)

DG No. 901

• Timing (Cycle Time)

8ns; tAC = 6.5ns @ CL = 3 ( tRP - 24ns) -8

10ns; tAC = 9ns @ CL = 2

-10

• Operating Temperature Ranges

-Military (-55°C to +125° C)

XT

-Industrial Temp (-40°C to 85° C)

IT

PIN ASSIGNMENT

(Top View)

54-Pin TSOP

Note: “\” indicates an active low.

4 Meg x 16

Configuration

1 Meg x 16 x 4 banks

Refresh Count

4K

Row Addressing

4K (A0-A11)

Bank Addressing

4 (BA0, BA1)

Column Addressing

256 (A0-A7)

KEY TIMING PARAMETERS

SPEED

GRADE

-8

-10

-8

-10

CLOCK

ACCESS TIME

FREQUENCY CL = 2** CL = 3**

125 MHz

–

6.5ns

100 MHz

–

7ns

83 MHz

9ns

–

66 MHz

9ns

–

SETUP

TIME

2ns

3ns

2ns

3ns

*Off-center parting line

**CL = CAS (READ) latency

HOLD

TIME

1ns

1ns

1ns

1ns

For more products and information

please visit our web site at

www.austinsemiconductor.com

AS4SD4M16

Rev. 1.5 10/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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