GS9021A 데이터 시트보기 (PDF) - Gennum -> Semtech

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GS9021A

EDH Coprocessor

Gennum -> Semtech 

If the HOST interface is not going to be used, the best way

to set the related pins is as follows:

HOSTIF_MODE = LOW

CS = HIGH

R/W = HIGH

A/D = DON'T CARE (BUT NOT FLOATING)

P[7:0] = N/C

5.1 I²C Serial Interface

PIN

SCL

SDA

A[2:0]

LOGIC OPR

HOST BIT

The I²C interface consists of a bi-directional serial data pin

(SDA) and a serial clock input pin (SCL). In addition, 3 input

pins, A[2:0] are provided to assign the chip one of eight

possible I²C addresses (0001A2A1A0).

During an I²C write operation, the first byte written to the

chip (after the device has been addressed) is interpreted

as the starting HOSTIF write table address for the

communication. The next byte is interpreted as data to be

written to the specified address. The address then

automatically increments so that the following bytes are

written to subsequent addresses.

When executing a read operation, a write must be per-

formed first to load the desired starting address. After this,

bytes read from the chip will begin at this address and will

auto-increment. If the read operation is halted and

communication with the chip is later established for another

read, the chip will resume reading at the next HOSTIF

memory address.

In I²C mode, P[7:5] and A/D must be set LOW while R/W

and CS must be set HIGH.

5.2 Parallel Interface

PIN

P[7:0]

A/D

R/W

CS

LOGIC OPR

HOST BIT

The asynchronous parallel interface consists of an 8-bit

multiplexed address/data bus (P[7:0]), a chip select pin

(CS), a read/write pin (R/W), and an address/data pin (A/D).

The following should be noted when interfacing to the

parallel port:

A) Read/Write cycles via the parallel interface are

completely independent and asynchronous to the

parallel clock PCLKIN.

B) Signals are "strobed" into/out of the parallel port on the

falling edge of the CS signal. Setup and hold times, as

defined in the AC timing tables, are relative to this edge

and must be met (see Figure 8a)

C) The GS9021A drives the P[7:0] bus when the R/W pin is

HIGH and the CS pin is LOW. At all other times, the

P[7:0] port is in a high impedance state. The host

interface enable and disable times are shown in Figure

8b and are specified in the AC timing information. In this

figure, the rising/falling edges of R/W and CS are not

aligned to illustrate that the state of the P[7:0] I/Os is

only a combinatorial function of the R/W and CS pins.

A write cycle to the parallel interface is shown in Figure 8c.

The starting address of the operation is written to the chip

by putting the R/W pin LOW (indicating write) and the A/D

pin high (indicating ADDRESS). At t0, the falling edge of CS

strobes in the information. Following this, the A/D line

should be asserted LOW indicating data. The R/W line

remains LOW indicating a write operation and at t1 the data

is strobed into the device.

A read example follows the write cycle. Note that the read

cycle begins with a write operation to indicate the starting

address. At t2, R/W is LOW (indicating write), A/D is HIGH

(indicating address) and P[7:0] represent the starting

address for the read cycle. After sufficient hold time, the

microcontroller releases the P[7:0] bus and the R/W is

asserted HIGH to indicate a read operation. At t3, the CS is

asserted low causing the GS9021A to present the required

data on the P[7:0] bus.

If two consecutive data read/write operations are

performed, the device will automatically increment the

address. However, for a completely random-access

operation, the address can be specified prior to every data

read/write operation.

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