H5DU2562GFR-XXI 데이터 시트보기 (PDF) - Hynix Semiconductor

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H5DU2562GFR-XXI

256Mb DDR SDRAM

Hynix Semiconductor 

H5DU2562GFR-xxI

IDD SPECIFICATION AND CONDITIONS (TA=-40 to 85 oC, Voltage referenced to VSS = 0V)

Test Conditions

Test Condition

Operating Current:

One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock

cycle; address and control inputs changing once per clock cycle

Operating Current:

One bank; Active - Read - Precharge;

Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle

Precharge Power Down Standby Current:

All banks idle; Power down mode; CKE=Low, tCK=tCK(min)

Idle Standby Current:

/CS=High, All banks idle; tCK=tCK(min);

CKE=High; address and control inputs changing once per clock cycle.

VIN=VREF for DQ, DQS and DM

Idle Quiet Standby Current:

/CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses and other control inputs stable, Vin=Vref for DQ, DQS

and DM

Active Power Down Standby Current:

One bank active; Power down mode; CKE=Low, tCK=tCK(min)

Active Standby Current:

/CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min);

DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock

cycle

Operating Current:

Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle;

tCK=tCK(min); IOUT=0mA

Operating Current:

Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle;

tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle

Auto Refresh Current:

tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh

tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz

Self Refresh Current:

CKE =< 0.2V; External clock on; tCK=tCK(min)

Operating Current - Four Bank Operation:

Four bank interleaving with BL=4

Symbol

IDD0

IDD1

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

IDD6

IDD7

Rev. 1.1 /Sep. 2007

17

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