HB28H016MM2 데이터 시트보기 (PDF) - Renesas Electronics

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HB28H016MM2

MultiMediaCard™ 16 MByte/32 MByte/64 MByte/128 MByte

Renesas Electronics 

;;;;;Clock

Input

tWH

tIH

Valid data

Output

tOH

HB28H016/D032/B064/B128MM2

tPP

tWL

tHL

tLH

Valid data

tISU

Valid data

tOSU

VIH

VIL

VIH

VIL

VOH

VOL

: Invalid

Timing Diagram of Data Input and Output

The access time (tAT) is divided into two parts:

• TSAD: The synchronous access time. This time defines the time of the maximum number of cycles

which are required to access a byte of the memory field.

• TAAD: The asynchronous access time to read a byte out of the memory field.

The synchronous part of the access time is sum of the command frame length and some additional internal

cycles (NSAD = 16 cycles). At 20 MHz one cycle is 50 ns (1/fPP), multiplied with NSAD the resulting frame

time is TSAD = 0.8 µs. The asynchronous access delay of these Hitachi MultiMediaCards is TAAD = 300 µs

maximum. The resulting memory access time tAT is the sum of both parts:

t =T +T

AT

AAD

SAD

with

T = N /f

SAD

SAD PP

CMD

command frame

TSAD

tAT

TAAD

response frame

DAT

data

Access Time

Rev.5.0, Jan. 2003, page 83 of 88

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