HD49340F 데이터 시트보기 (PDF) - Renesas Electronics

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HD49340F

CDS/PGA & 10-bit A/D Converter

Renesas Electronics 

HD49340F/HF

Operation Sequence at Power On

VDD

Start control

of TG and

camera DSP

SPBLK

SPSIG

ADCLK

etc.

OBP

Must be stable within the operating

power supply voltage range

1 ms or more High-speed pulse is the right phase

Prohibition

period

OBP is started within this period

OBP is the right phase

HD49340F/HF

serial data transfer

RESET bit

2 ms or more

(1) Register 2 setting

0 ms

or more

(3) Registers 0

(2) Register 2 setting

and 1 settings

2 ms or more

RESET = "Low"

(RESET mode)

RESET = "High"

(RESET cancellation)

Automatic offset

calibration

(4)Offset calibration

(automatically starts

after RESET

cancellation)

Ends after

40000 clock cycles

The following describes the above serial data transfer. For details on registers 0, 1, and 2, refer to table 10.

(1) Register 2 setting

: Set all bits in register 2 to the usage condition, and set the RESET bit to low.

(2) Register 2 setting

: Cancel the RESET mode by setting the register 2 RESET bit to high.

Do not change other register 2 settings. Offset calibration starts automatically.

(3) Register 0 and 1 settings : After the offset calibration is terminated, set registers 0 and 1.

(4) Please perform an offset calibration in the period which avoided PBLK of V.

Rev.1.0, Apr 20, 2004, page 19 of 22

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