HIP0060 데이터 시트보기 (PDF) - Intersil

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HIP0060

1.5A, 50V Quad Low Side Power Driver with Serial Bus Control and Fault Protection

Intersil 

Timing Diagrams

HIP0060

CS

SCK

(CPOL = 0, CPHA = 1)

MSB 6

5

4

3

2

1

LSB

INTERNAL STROBE FOR DATA CAPTURE

FIGURE 4. DATA AND CLOCK TIMING DIAGRAM

CS

tLEAD

tCYC

tfSCK

trSCK

tLAG

SCK

SI

tWSCKH

tWSCKL

tSU

DI7

DI6

DI1

D10

SO

(THREE-STATE)

DO7

tV

DO6

DO1

tDIS

DO0

FIGURE 5. BYTE TIMING DIAGRAM WITH ASYNCHRONOUS RESET. REFER TO THE ELECTRICAL SPECIFICATION FOR THE

HIGH AND LOW INPUT AND OUTPUT THRESHOLD LEVELS SHOWN FOR TIMING REFERENCE

6

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