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HEF4022B

4-stage divide-by-8 Johnson counter

Philips Electronics 

Philips Semiconductors

4-stage divide-by-8 Johnson counter

Product specification

HEF4022B

MSI

DESCRIPTION

The HEF4022B is a 4-stage divide-by-8 Johnson counter

with eight spike-free decoded active HIGH outputs (O0 to

O7), an active LOW output from the most significant

flip-flop (O4-7), active HIGH and active LOW clock inputs

(CP0, CP1) and an overriding asynchronous master reset

input (MR).

The counter is advanced by either a LOW to HIGH

transition at CP0 while CP1 is LOW or a HIGH to LOW

transition at CP1 while CP0 is HIGH (see also function

table). Either CP0 or CP1 may be used as clock input to the

counter and the other clock input may be used as a clock

enable input. When cascading counters, the O4-7 output,

which is LOW while the counter is in states, 4, 5, 6 and 7,

can be used to drive the CP0 input of the next counter.

A HIGH on MR resets the counter to zero

(O0 = O4-7 = HIGH; O1 to O7 = LOW) independent of the

clock inputs (CP0, CP1).

Automatic code correction of the counter is provided by an

internal circuit, following any illegal code the counter

returns to a proper counting mode within 11 clock pulses.

Fig.1 Functional diagram.

PINNING

CPO

CP1

MR

O0 to O7

O4-7

Fig.2 Pinning diagram.

HEF4022BP(N): 16-lead DIL; plastic

(SOT38-1)

HEF4022BD(F): 16-lead DIL; ceramic (cerdip)

(SOT74)

HEF4022BT(D): 16-lead SO; plastic

(SOT109-1)

( ): Package Designator North America

FAMILY DATA, IDD LIMITS category MSI

See Family Specifications

clock input (LOW to HIGH; edge-triggered)

clock input (HIGH to LOW; edge-triggered)

master reset input

decoded outputs

carry output (active LOW)

January 1995

2

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