HM5116100 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics
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HM5116100 Datasheet PDF : 24 Pages
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HM5116100 Series
Notes: 1. AC measurements assume tT = 5 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If
the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are
required.
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
6. Assume that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
7. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
8. Assume that tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max).
9. Assume that tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max).
10. Either tRCH or tRRH must be satisfied for a read cycles.
11. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
12. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD
≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥
tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
13. These parameters are referenced to CAS leading edge in early write cycles and to WE leading
edge in delayed write or read-modify-write cycles.
14. tRASP defines RAS pulse width in fast page mode cycles.
15. Access time is determined by the longest among tAA, tCAC and tCPA.
16. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0, CA1, CA10 and
CA11 for the 16M × 1 are don’t care during test mode. Test mode is set by performing a WE-
and-CAS-before-RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 16 bits in
parallel at Din and read out from Dout.
If 16 bits are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then
the device has passed. If they are not equal, data output pin is a low state, then the device has
failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR
refresh cycles.
To get out of test mode and enter a normal operation mode, perform either a regular CAS-
before-RAS refresh cycle or RAS-only refresh cycle.
17. In a test mode read cycle, the value of tRAC, tAA, tCAC and tCPA is delayed by 2 ns to 5 ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
18. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
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