HM6264BLPI 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics

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HM6264BLPI

64k SRAM (8-kword × 8-bit) Wide Temperature Range version

Hitachi -> Renesas Electronics 

HM6264BI Series

Low VCC Data Retention Characteristics (Ta = –40 to +85°C)

Parameter

Symbol Min Typ*1 Max Unit Test conditions*3

VCC for data retention

VDR

2.0 — — V

CS1 ≥ VCC –0.2 V,

CS2 ≥ VCC –0.2 V or CS2 ≤ 0.2 V

Vin ≥ 0 V

Data retention current

I CCDR

—

1*1

100*2 µA

VCC = 3.0 V, 0 V ≤ Vin ≤ VCC

CS1 ≥ VCC –0.2 V, CS2 ≥ VCC –0.2 V

or 0 V ≤ CS2 ≤ 0.2 V

Chip deselect to data

t CDR

0

— — ns See retention waveform

retention time

Operation recovery time tR

5

— — ms

Notes: 1. Reference data at Ta = 25°C.

2. 10 µA max at Ta = –40 to + 40°C.

3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls

data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If

CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The

other input levels (address, WE, OE, I/O) can be in the high impedance state.

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