HM628128ALR-8 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics

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HM628128ALR-8

131,072-word × 8-bit High Speed CMOS Static RAM

Hitachi -> Renesas Electronics 

HM628128A Series

data bus contention.

tWP ≥ tDW min + tWHZ max

Low VCC Data Retention Characteristics (Ta = 0 to +70°C)

Parameter

Symbol Min Typ Max Unit Test conditions*4

VCC for data retention VDR

2.0 —

—

V

CS1 ≥ VCC – 0.2 V,

CS2 ≥ VCC – 0.2 V or

0 V ≤ CS2 ≤ 0.2 V

Vin>0 V

Data retention current ICCDR

—

1

(L version)

ICCDR

—

1

(L-L version)

50*1 µA

30*2 µA

VCC = 3.0 V, Vin ≥ 0 V

CS1 ≥ VCC – 0.2V

CS2 ≥ VCC – 0.2 V or

0 V ≤ CS2 ≤ 0.2 V

ICCDR

(L-SL

—

1

version)

15*3 µA

Chip deselect to

data retention time

tCDR

0

—

—

ns

See retention waveform

Operation recovery time tR

5

—

—

ms

Low VCC Data Retention Timing Waveform (1) (CS1 Controlled)

t CDR

Data retention mode

tR

VCC

4.5 V

2.2 V

VDR1

CS1

0V

CS1 > VCC – 0.2 V

Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)

tCDR

Data retention mode

tR

VCC

4.5 V

CS2

VDR2

0.4 V

0V

0 V < CS2 < 0.2 V

12

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