HT48RA0-1 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT48RA0-1

Remote Type 8-Bit MCU

Holtek Semiconductor 

HT48RA0-1/HT48CA0-1

A.C. Characteristics

Symbol

Parameter

fSYS

System Clock

tRES

External Reset Low Pulse Width

tSST

System Start-up Timer Period

tLVR

Low Voltage Width to Reset

Test Conditions

VDD

Conditions

3V

¾

¾

¾

¾

Power-up, reset or wake-up

from HALT

¾

¾

Min.

400

1

¾

1

Note: tSYS=1/fSYS

Typ.

¾

¾

1024

¾

Ta=25°C

Max. Unit

4000 kHz

¾

ms

¾

tSYS

¾

ms

Functional Description

Execution Flow

The HT48RA0-1/HT48CA0-1 system clock can be de-

rived from a crystal/ceramic resonator oscillator. It is in-

ternally divided into four non-overlapping clocks. One

instruction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such

a way that a fetch takes one instruction cycle while de-

coding and execution takes the next instruction cycle.

However, the pipelining scheme causes each instruc-

tion to effectively execute within one cycle. If an instruc-

tion changes the program counter, two cycles are

required to complete the instruction.

Program Counter - PC

The 10-bit program counter (PC) controls the sequence

in which the instructions stored in program ROM are ex-

ecuted and its contents specify a maximum of 1024 ad-

dresses.

After accessing a program memory word to fetch an in-

struction code, the contents of the program counter are

incremented by one. The program counter then points to

the memory word containing the next instruction code.

When executing a jump instruction, conditional skip ex-

ecution, loading PCL register, subroutine call, initial re-

set or return from subroutine, the PC manipulates the

program transfer by loading the address corresponding

to each instruction.

The conditional skip is activated by instruction. Once the

condition is met, the next instruction, fetched during the

current instruction execution, is discarded and a dummy

cycle replaces it to get the proper instruction. Otherwise

proceed with the next instruction.

The lower byte of the program counter (PCL) is a read-

able and writeable register (06H). Moving data into the

PCL performs a short jump. The destination will be

within 256 locations.

When a control transfer takes place, an additional

dummy cycle is required.

Program Memory - ROM

The program memory is used to store the program in-

structions which are to be executed. It also contains

data and table and is organized into 1024´14 bits, ad-

dressed by the program counter and table pointer.

Certain locations in the program memory are reserved

for special usage:

· Location 000H

This area is reserved for the initialization program. Af-

ter chip reset, the program always begins execution at

location 000H.

Rev. 1.40

T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

S y s te m C lo c k

In s tr u c tio n C y c le

PC

PC

PC +1

PC +2

F e tc h IN S T (P C )

E x e c u te IN S T (P C -1 )

F e tc h IN S T (P C + 1 )

E x e c u te IN S T (P C )

F e tc h IN S T (P C + 2 )

E x e c u te IN S T (P C + 1 )

Execution Flow

4

December 21, 2005

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