48R01A3 데이터 시트보기 (PDF) - Holtek Semiconductor

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48R01A3

Small Package I/O Type 8-Bit OTP MCU

Holtek Semiconductor 

HT48R01A

Configuring the Event Counter Mode

In this mode, a number of externally changing logic

events, occurring on the external timer pin, can be re-

corded by the internal timer. For the timer to operate in

the event counting mode, the bit pair, T0M1/T0M0 must

be set to 0 and 1 respectively. The timer-on bit T0ON or

T1ON, depending upon which timer is used, must be set

high to enable the timer to count. If T0E is low, the coun-

ter will increment each time the external timer pin re-

ceives a low to high transition. If T0E is high, the counter

will increment each time the external timer pin receives

a high to low transition. As in the case of the other two

modes, when the counter is full, the timer will overflow

and generate an internal interrupt signal. The counter

will then preload the value already loaded into the

preload register. As the external timer pins are

pin-shared with other I/O pins, to ensure that the pin is

configured to operate as an event counter input pin, two

things have to happen. The first is to ensure that the

T0M1/T0M0 bits place the Timer/Event Counter in the

event counting mode, the second is to ensure that the

port control register configures the pin as an input. It

should be noted that a timer overflow is one of the inter-

rupt and wake-up sources. Note that the timer interrupts

can be disabled by ensuring that the ET0I bits in the

INTC0 register are reset to zero.

Configuring the Pulse Width Measurement Mode

In this mode, the width of external pulses applied to the

external timer pin can be measured. In the Pulse Width

Measurement Mode the timer clock source is supplied

by the internal clock. For the timer to operate in this

mode, the bit pair, T0M1/T0M0 must both be set high. If

the T0E bit is low, once a high to low transition has been

received on the external timer pin, the timer will start

counting until the external timer pin returns to its original

high level. At this point the T0ON bit will be automatically

reset to zero and the timer will stop counting. If the T0E

bit is high, the timer will begin counting once a low to

high transition has been received on the external timer

pin and stop counting when the external timer pin re-

turns to its original low level. As before, the T0ON bit will

be automatically reset to zero and the timer will stop

counting. It is important to note that in the Pulse Width

Measurement Mode, the T0ON bit is automatically reset

to zero when the external control signal on the external

timer pin returns to its original level, whereas in the other

two modes the T0ON bit can only be reset to zero under

program control. The residual value in the timer, which

can now be read by the program, therefore represents

the length of the pulse received on the external timer

pin. As the T0ON bit has now been reset, any further

transitions on the external timer pin, will be ignored. Not

until the T0ON bit is again set high by the program can

the timer begin further pulse width measurements. In

this way, single shot pulse measurements can be easily

made. It should be noted that in this mode the counter is

controlled by logical transitions on the external timer pin

and not by the logic level. As in the case of the other two

modes, when the counter is full, the timer will overflow

and generate an internal interrupt signal. The counter

will also be reset to the value already loaded into the

preload register. If the external timer pin is pin-shared

with other I/O pins, to ensure that the pin is configured to

operate as a pulse width measuring input pin, two things

have to happen. The first is to ensure that the

T0M1/T0M0 bits place the Timer/Event Counter in the

pulse width measuring mode, the second is to ensure

that the port control register configures the pin as an in-

put. It should be noted that a timer overflow and corre-

sponding timer interrupt is one of the wake-up sources.

Note that the timer interrupts can be disabled by ensur-

ing that the ET0I bits in the INTC0 register are reset to

zero.

E x te rn a l E v e n t

In c re m e n t

T im e r C o u n te r

T im e r + 1

T im e r + 2

Event Counter Mode Timing Chart

T im e r + 3

E x te r n a l T im e r

P in In p u t

T0O N orT1O N

( w ith T 0 E o r T 1 E = 0 )

P r e s c a le r O u tp u t

In c re m e n t

T im e r C o u n te r

T im e r

+1

+2

+3

+4

P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .

Pulse Width Measure Mode Timing Chart

Rev. 1.10

19

August 4, 2008

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