HT48R065B 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT48R065B Datasheet PDF : 86 Pages
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HT48R063B/064B/065B/066B
Ta=25°C
Symbol
Parameter
Test Conditions
VDD
Conditions
5V Ta=25°C, R=120kW *
Min. Typ. Max. Unit
-2%
4
+2% MHz
5V Ta=0~70°C, R=120kW * -5%
4
+5% MHz
fERC
System Clock (ERC)
5V Ta= -40°C~85°C,
R=120kW *
-7%
4
+7% MHz
fLXT
System Clock (LXT)
fTIMER
Timer Input Frequency
(TCn)
2.2V~ Ta= -40°C~85°C,
5.5V R=120kW *
¾
¾
2.2V~5.5V
¾ 3.0V~5.5V
4.5V~5.5V
-11% 4 +11% MHz
¾ 32768 ¾
Hz
0
¾ 4000 kHz
0
¾ 8000 kHz
0
¾ 12000 kHz
fLIRC
tRES
tSST
LIRC Oscillator
External Reset Low Pulse Width
System Start-up time Period
3V
¾
5
5V
¾
6.5
¾
¾
1
For HXT/LXT
¾
¾ For ERC/IRC
(By configuration option)
¾
10
15 kHz
13 19.5 kHz
¾
¾
ms
128
¾
tSYS
2
¾
tSYS
tINT
Interrupt Pulse Width
¾
tLVR
Low Voltage Width to Reset
¾
RESTD Reset Delay Time
¾
¾
1
¾
¾
ms
¾
0.25
1
2
ms
¾
¾
100
¾
ms
Note:
1. tSYS=1/fSYS
2. *For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended.
3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
Power-on Reset Characteristics
Symbol
Parameter
Test Conditions
VDD
Conditions
VPOR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
RRVDD
VDD raising rate to Ensure
Power-on Reset
¾
¾
tPOR
Minimum Time for VDD Stays at
VPOR to Ensure Power-on Reset
¾
¾
Min. Typ. Max. Unit
¾
¾ 100 mV
0.035 ¾
¾ V/ms
1
¾
¾
ms
V DD
tP O R
R R VDD
V POR
T im e
Rev. 1.10
14
October 23, 2012
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