HT48R0662 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT48R0662 Datasheet PDF : 96 Pages
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HT48R063/064/065/066/0662/067
Ta=25°C
Symbol
Parameter
fLXT
System Clock (LXT)
Test Conditions
VDD
Conditions
¾
¾
Min. Typ. Max. Unit
¾ 32768 ¾
Hz
fTIMER
Timer Input Frequency
(TCn)
2.2V~5.5V
¾ 3.0V~5.5V
4.5V~5.5V
0
¾ 4000 kHz
0
¾ 8000 kHz
0
¾ 12000 kHz
fLIRC
LIRC Oscillator
3V
¾
5
10
15 kHz
5V
¾
6.5
13 19.5 kHz
tRES
External Reset Low Pulse Width ¾
¾
1
¾
¾
ms
For HXT/LXT
¾ 1024 ¾
tSYS
tSST
System Start-up time Period
¾ For ERC/IRC
¾
2
¾
tSYS
(By configuration option) ¾ 1024 ¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
RESTD Reset Delay Time
¾
¾
¾
100
¾
ms
Note:
1. tSYS=1/fSYS
2. *For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended.
3. For the HT48R064 device, the fERC parameter is not applicable.
4. For the HT48R064 device, the HIRC support 4MHz only and fHIRC parameter of (5V, 3.0V~5.5V) is
applicable.
5. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
Power-on Reset Characteristics
Symbol
Parameter
Test Conditions
VDD
Conditions
VPOR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
RRVDD
VDD raising rate to Ensure
Power-on Reset
¾
¾
tPOR
Minimum Time for VDD Stays at
VPOR to Ensure Power-on Reset
¾
¾
Min. Typ. Max. Unit
¾
¾ 100 mV
0.035 ¾
¾ V/ms
1
¾
¾
ms
V DD
tP O R
R R VDD
V POR
T im e
Rev. 1.40
12
October 23, 2012
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