HT46R01 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT46R01

10-Pin MSOP A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R01/HT46R02/HT46R03

D a ta B u s

P r e lo a d R e g is te r

R e lo a d

fS Y S /4

R T C O s c illa to r

M

U

X

T1S

TM R 1

T1M 1 T1M 0

T im e r /E v e n t C o u n te r

M o d e C o n tro l

T1O N

T im e r /E v e n t C o u n te r

¸2

O v e r flo w

to In te rru p t

PFD

T1E

8-bit Timer/Event Counter 1 Structure - HT46R02 and HT46R03

Timer Registers - TMR0, TMR1

The timer registers are special function registers located

in the Special Purpose Data Memory and is the place

where the actual timer value is stored. These registers

are known as TMR0 or TMR1, depending upon which de-

vice is used. The value in the timer registers increases by

one each time an internal clock pulse is received or an

external transition occurs on the external timer pin. The

timer will count from the initial value loaded by the

preload register to the full count of FFH at which point the

timer overflows and an internal interrupt signal is gener-

ated. The timer value will then be reset with the initial

preload register value and continue counting.

Note that to achieve a maximum full range count of FFH,

the preload register must first be cleared to all zeros. It

should be noted that after power-on, the preload regis-

ters will be in an unknown condition. Note that if the

Timer/Event Counters are in an OFF condition and data

is written to their preload registers, this data will be im-

mediately written into the actual counter. However, if the

counter is enabled and counting, any new data written

into the preload data registers during this period will re-

main in the preload registers and will only be written into

the actual counter the next time an overflow occurs.

Timer Control Registers - TMR0C, TMR1C

The flexible features of the Holtek microcontroller

Timer/Event Counters enable them to operate in three

different modes, the options of which are determined by

the contents of their respective control register.

For devices with only one timer, the single Timer Control

Register is known as TMR0C while for devices with

more than one timer, there are two Timer Control Regis-

ters, known as TMR0C and TMR1C. It is the Timer Con-

trol Register together with its corresponding timer

registers that control the full operation of the

b7

T0M 1 T0M 0 T0S T0O N T0E

b0

T0P S C 2 T0P S C 1 T0P S C 0

T im e r /E v e n t C o u n te r C o n tr o l R e g is te r

T M R 0 C A ll D e v ic e s

T im e r p r e s c a le r r a te s e le c t

T0P S C 2

0

0

0

0

1

1

1

1

T0P S C 1

0

0

1

1

0

0

1

1

T0P S C 0

0

1

0

1

0

1

0

1

T im e r R a te

1 :1

1 :2

1 :4

1 :8

1 :1 6

1 :3 2

1 :6 4

1 :1 2 8

E v e n t C o u n te r a c tiv e e d g e s e le c t

1 : c o u n t o n fa llin g e d g e

0 : c o u n t o n r is in g e d g e

P u ls e W id th M e a s u r e m e n t a c tiv e e d g e s e le c t

1 : s ta r t c o u n tin g o n r is in g e d g e , s to p o n fa llin g e d g e

0 : s ta r t c o u n tin g o n fa llin g e d g e , s to p o n r is in g e d g e

T im e r /E v e n t C o u n te r c o u n tin g e n a b le

1 : e n a b le

0 : d is a b le

T im e r c lo c k s o u r c e

1:R TC

0 : fS Y S

O p e r a tin g m o d e s e le c t

T0M 1

0

0

1

1

T0M 0

0

1

0

1

n o m o d e a v a ila b le

e v e n t c o u n te r m o d e

tim e r m o d e

p u ls e w id th m e a s u r e m e n t m o d e

Rev. 1.00

19

September 21, 2007

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