HT46R24 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT46R24 Datasheet PDF : 51 Pages
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HT46R24/HT46C24
PW M
(6 + 2 ) o r (7 + 1 )
C o m p a re
T o P D 0 /P D 1 /P D 2 /P D 3 C ir c u it
fS Y S
8 - s ta g e P r e s c a le r
fIN T
8 -1 M U X
T0P S C 2~T0P S C 0 TM R 0
T0M 1
T0M 0
T0E
L o w B y te
B u ffe r
1 6 - B it
P r e lo a d R e g is te r
D a ta B u s
R e lo a d
T0M 1
T0M 0
T0O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
H ig h B y te L o w B y te
1 6 - B it T im e r /E v e n t C o u n te r
PFD 0
Timer/Event Counter 0
O v e r flo w to In te r r u p t
D a ta B u s
fS Y S /4
TM R 1
f IN T
T1M 1
T1M 0
T1E
T1M 1
T1M 0
T1O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
L o w B y te
B u ffe r
1 6 - B it
P r e lo a d R e g is te r
R e lo a d
H ig h B y te L o w B y te
1 6 - B it T im e r /E v e n t C o u n te r
PFD 1
Timer/Event Counter 1
O v e r flo w to In te r r u p t
PFD 0
PFD 1
M
U
1 /2
PFD
X
P A 3 D a ta C T R L
P F D S o u r c e O p tio n
PFD Source Option
To enable the counting operation, the Timer ON bit
(T0ON: bit 4 of TMR0C; T10N: bit 4 of TMR1C) should
be set to 1. In the pulse width measurement mode, the
T0ON/T1ON is automatically cleared after the measure-
ment cycle is completed. But in the other two modes, the
T0ON/T1ON can only be reset by instructions. The
overflow of the Timer/Event Counter 0/1 is one of the
wake-up sources and can also be applied to a PFD (Pro-
grammable Frequency Divider) output at PA3 by op-
tions. Only one PFD (PFD0 or PFD1) can be applied to
PA3 by options. If PA3 is set as PFD output, there are
two types of selections; One is PFD0 as the PFD output,
the other is PFD1 as the PFD output. PFD0, PFD1 are
the timer overflow signals of the Timer/Event Counter 0,
Timer/Event Counter 1 respectively. No matter what the
operation mode is, writing a 0 to ET0I or ET1I disables
the related interrupt service. When the PFD function is
selected, executing ²SET [PA].3² instruction to enable
PFD output and executing ²CLR [PA].3² instruction to
disable PFD output.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also re-
loads that data to the timer/event counter. But if the
timer/event counter is turn on, data written to the
timer/event counter is kept only in the timer/event coun-
ter preload register. The timer/event counter still contin-
ues its operation until an overflow occurs.
When the timer/event counter (reading TMR0/TMR1) is
read, the clock is blocked to avoid errors, as this may re-
sults in a counting error. Blocking of the clock should be
taken into account by the programmer. It is strongly rec-
ommended to load a desired value into the TMR0/TMR1
register first, before turning on the related timer/event
counter, for proper operation since the initial value of
TMR0/TMR1 is unknown. Due to the timer/event
scheme, the programmer should pay special attention
on the instruction to enable then disable the timer for the
first time, whenever there is a need to use the
timer/event function, to avoid unpredictable result. After
this procedure, the timer/event function can be operated
normally.
Rev. 2.00
15
March 2, 2006
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