HT46R24 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT46R24 Datasheet PDF : 51 Pages
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HT46R24/HT46C24
Input/Output Ports
There are 40 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC, PD and PF,
which are mapped to the data memory of [12H], [14H],
[16H], [18H] and [28H] respectively. All of these I/O ports
can be used for input and output operations. For input
operation, these ports are non-latching, that is, the in-
puts must be ready at the T2 rising edge of instruction
²MOV A,[m]² (m=12H, 14H, 16H, [18H] or 28H). For out-
put operation, all the data is latched and remains un-
changed until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC, PFC) to control the input/output configura-
tion. With this control register, CMOS output or Schmitt
trigger input with or without pull-high resistor structures
can be reconfigured dynamically under software control.
To function as an input, the corresponding latch of the
control register must write ²1². The input source also de-
pends on the control register. If the control register bit is
²1², the input will read the pad state. If the control regis-
ter bit is ²0², the contents of the latches will move to the
internal bus. The latter is possible in the ²read-modify-
write² instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H, 19H and 29H.
After a chip reset, these input/output lines remain at high
levels or floating state (depends on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
16H 18H or 28H) instructions.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device. Each I/O port has a pull-high option. Once the
pull-high option is selected, the I/O port has a pull-high
resistor, otherwise, there¢s none. Take note that a
non-pull-high I/O port operating in input mode will cause
a floating state.
The PA3 and PA5 are pin-shared with the PFD and INT
pins respectively. If the PFD option is selected, the out-
put signal in output mode of PA3 will be the PFD signal
generated by timer/event counter overflow signal. The
input mode always remain in its original functions. Once
the PFD option is selected, the PFD output signal is con-
trolled by PA3 data register only. Writing ²1² to PA3 data
register will enable the PFD output function and writing 0
will force the PA3 to remain at ²0². The I/O functions of
PA3 are shown below.
I/O
I/P
O/P
Mode (Normal) (Normal)
PA3
Logical
Input
Logical
Output
I/P
(PFD)
O/P
(PFD)
Logical
PFD
Input (Timer on)
Note: The PFD frequency is the timer/event counter
overflow frequency divided by 2.
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0/PD1/PD2/PD3. If the PWM
function is enabled, the PWM0/PWM1/PWM2/PWM3
signal will appear on PD0/PD1/PD2/PD3 (if PD0/PD1/
PD2/PD3 is operating in output mode). The I/O func-
tions of PD0/PD1/PD2/PD3 are as shown.
D a ta B u s
W r ite C o n tr o l R e g is te r
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
[P A 3 , P F D ]
o r [P D 0 ,P W M 0 ]
o r [P D 1 ,P W M 1 ]
o r [P D 2 ,P W M 2 ]
o r [P D 3 ,P W M 3 ]
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly )
IN T fo r P A 5 O n ly
C o n tr o l B it
DQ
CK Q
S
D a ta B it
DQ
CK Q
S
M
U
X
V DD
PU
M
U
X
E N (P F D o r
P W M 0~P W M 3)
P A 0~P A 2
P A 3 /P F D
PA4
P A 5 /IN T
P A 6 /S D A
P A 7 /S C L
P B 0 /A N 0 ~ P B 7 /A N 7
P C 0~P C 7
P D 0 /P W M 0
P D 1 /P W M 1
P D 2 /P W M 2
P D 3 /P W M 3
P D 4~P D 7
P F0~P F7
O P 0~O P 7
Input/Output Ports
Rev. 2.00
17
March 2, 2006
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