HT46R343 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT46R343 Datasheet PDF : 40 Pages
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HT46R343
Bit No.
0
1~3
4
5~7
Label
EADI
¾
ADF
¾
Function
Control the A/D converter interrupt (1=enabled; 0=disabled)
Unused bit, read as ²0²
A/D converter request flag (1=active; 0=inactive)
Unused bit, read as ²0²
INTC1 (1EH) Register
All interrupts have a wake-up capability. As an interrupt
is serviced, a control transfer occurs by pushing the pro-
gram counter onto the stack, followed by a branch to a
subroutine at a specified location in the program mem-
ory. Only the program counter is pushed onto the stack.
If the contents of the register or status register are al-
tered by the interrupt service program which corrupts
the desired control sequence, the contents should be
saved in advance.
External interrupts are triggered by a high to low transi-
tion on the INT pin, which will set the related interrupt re-
quest flag, EIF, which is bit 4 of INTC0. When the
interrupt is enabled, the stack is not full and the external
interrupt is active, a subroutine call to location 04H will
occur. The interrupt request flag, EIF, and EMI bits will
be cleared to disable other interrupts.
The internal timer/event counter 0 interrupt is initialised
by setting the timer/event counter interrupt request flag,
T0F, which is bit 5 of INTC0, caused by a timer overflow.
When the interrupt is enabled, the stack is not full and
the T0F bit is set, a subroutine call to location 008H will
occur. The related interrupt request flag, T0F, will be re-
set and the EMI bit cleared to disable further interrupts.
The internal timer/event counter 1 interrupt is initialised
by setting the timer/event counter interrupt request flag,
T1F, which is bit 6 of INTC1, caused by a timer overflow.
When the interrupt is enabled, the stack is not full and
the T1F bit is set, a subroutine call to location 00CH will
occur. The related interrupt request flag, T1F, will be re-
set and the EMI bit cleared to disable further interrupts.
The A/D converter interrupt is initialised by setting the
A/D converter request flag, ADF, which is bit 4 of INTC1,
caused by an end of A/D conversion. When the interrupt
is enabled, the stack is not full and the ADF bit is set, a
subroutine call to location 010H will occur. The related
interrupt request flag, ADF, will be reset and the EMI bit
cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1. Of course, the stack
must not be full. To return from the interrupt subroutine,
a RET or RETI instruction may be executed. A RETI in-
struction will set the EMI bit to enable an interrupt ser-
vice, but a RET instruction will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority Vector
External Interrupt
1
004H
Timer/Event Counter 0 Overflow
2
008H
Timer/Event Counter 1 Overflow
3
00CH
A/D Converter Interrupt
4
010H
Once the interrupt request flags, T0F/T1F, EIF, ADF, are
set, they will remain in the INTC0/INTC1 register until
the interrupts are serviced or cleared by a software in-
struction. It is recommended that a program does not use
the CALL subroutine within the interrupt subroutine. Inter-
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well con-
trolled, the original control sequence will be damaged
once the ²CALL² operates in the interrupt subroutine.
Oscillator Configuration
There are two oscillator circuits in the microcontroller,
namely an RC oscillator and a crystal oscillator, the
choice of which is determined by a configuration option.
When the system enters the Power-down mode the sys-
tem oscillator stops and ignores external signals to con-
serve power.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required whose resistance value
must range from 24kW to 1MW. The system clock, di-
vided by 4, can be monitored on pin OSC2 if a pull-high
resistor is connected. This signal can be used to syn-
chronise external logic. The RC oscillator provides the
most cost effective solution, however the frequency of
O SC1
V DD
470pF
O SC1
O SC2
fS Y S /4
O SC2
C r y s ta l O s c illa to r
R C O s c illa to r
System Oscillator
Rev. 1.00
11
October 11, 2007
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