HT46R65-56 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT46R65-56

(HT46R063B - HT46R065B) Enhanced A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

Reset

There are three ways in which reset may occur.

· RES is reset during normal operation

· RES is reset during HALT

· WDT time-out is reset during normal operation

The WDT time-out during HALT differs from other chip

reset conditions, for it can perform a ²warm reset² that

resets only the program counter and SP and leaves the

other circuits at their original state. Some registers re-

main unaffected during any other reset conditions. Most

registers are reset to the ²initial condition² once the re-

set conditions are met. Examining the PDF and TO

flags, the program can distinguish between different

²chip resets².

TO PDF

RESET Conditions

0 0 RES reset during power-up

u u RES reset during normal operation

0 1 RES Wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT Wake-up HALT

Note: ²u² stands for unchanged

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem awakes from the HALT state or during power up.

Awaking from the HALT state or system power-up, the

SST delay is added.

An extra SST delay is added during the power-up pe-

riod, and any wake-up from HALT may enable only the

SST delay.

The functional unit chip reset status is shown below.

Program Counter 000H

Interrupt

Disabled

Prescaler, Divider Cleared

WDT, RTC,

Time Base

Cleared. After master reset,

WDT starts counting

Timer/event Counter Off

Input/output Ports Input mode

Stack Pointer

Points to the top of the stack

HT46R65/HT46C65

V DD

0 .0 1 m F *

100kW

RES

10kW

0 .1 m F *

Reset Circuit

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

VDD

RES

S S T T im e - o u t

C h ip R e s e t

tS S T + tO P D

Reset Timing Chart

H A LT

W DT

RES

W DT

T im e - o u t

R eset

O SC1

SST

1 0 - b it R ip p le

C o u n te r

E x te rn a l

W a rm R e s e t

C o ld

R eset

P o w e r - o n D e te c tio n

Reset Configuration

Rev. 1.80

15

July 14, 2005

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