HT49R30 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT49R30 Datasheet PDF : 43 Pages
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HT49R30A-1/HT49C30-1/HT49C30L
The functional unit chip reset status is shown below.
PC
000H
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT, RTC, Time Base
Cleared. After master reset,
WDT starts counting
Timer/Event Counter Off
Input/output Ports
Input mode
SP
Points to the top of the stack
VDD
RES
S S T T im e - o u t
C h ip R e s e t
tO P D + tS S T
Reset timing chart
H A LT
W DT
RES
W DT
T im e - o u t
R eset
O SC1
SST
1 0 - b it R ip p le
C o u n te r
E x te rn a l
P o w e r - o n D e te c tio n
W a rm R e s e t
C o ld
R eset
Reset configuration
The states of the registers are summarized below:
Register
Reset (Power On)
WDT Time-out
(Norma Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
TMR
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu uuuu uuuu
TMRC
0000 1---
0000 1---
0000 1---
0000 1---
uuuu u---
Program Counter
0000H
0000H
0000H
0000H
0000H
MP0
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
MP1
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
BP
---- ---0
---- ---0
---- ---0
---- ---0
---- ---u
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTC1
--00 --00
--00 --00
--00 --00
--00 --00
--uu --uu
RTCC
--00 0111
--00 0111
--00 0111
--00 0111
--uu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111 uuuu uuuu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.10
16
September 25, 2002
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