HT49R30 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT49R30 Datasheet PDF : 43 Pages
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HT49R30A-1/HT49C30-1/HT49C30L
Label
(TMR0C)
Bits
Function
¾
0~2 Unused bit, read as ²0²
TE
3
To define the TMR0 active edge of timer/event counter
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer counting
(0=disabled; 1=enabled)
TN2
5
2 to 1 multiplexer control inputs to select the timer/event counter clock source
(0=RTC outputs; 1= system clock or system clock/4)
To define the operating mode (TN1, TN0)
TN0
TN1
6
7
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TMRC register
It is strongly recommended to load a desired value into
the TMR register first, then turn on the related
timer/event counter for proper operation, because the
initial value of TMR is unknown.
Due to the timer/event scheme, the programmer should
pay special attention on the instruction to enable then
disable the timer for the first time, whenever there is a
need to use the timer/event function, to avoid unpredict-
able result. After this procedure, the timer/event function
can be operated normally.
Input/output ports
There are a 8-bit bidirectional input/output port, an 6-bit
input port in the device, labeled PA, PB which are
mapped to [12H], [14H] of the RAM, respectively.
PA0~PA3 can be configured as CMOS (output) or
NMOS (input/output) with or without pull-high resistor by
options. PA4~PA7 are always pull-high and NMOS (in-
put/output).
If you choose NMOS (input), each bit on the port
(PA0~PA7) can be configured as a wake-up input. PB
can only be used for input operation. All the ports for the
input operation (PA, PB), are non-latched, that is, the in-
puts should be ready at the T2 rising edge of the instruc-
tion ²MOV A, [m]² (m=12H or 14H).
For PA output operation, all data are latched and remain
unchanged until the output latch is rewritten.
When the PA structures are open drain NMOS type, it
should be noted that, before reading data from the pads,
a ²1² should be written to the related bits to disable the
NMOS device. That is executing first the instruction
²SET [m].i² (i=0~7 for PA) to disable related NMOS de-
vice, and then ²MOV A, [m]² to get stable data.
After chip reset, these input lines remain at the high level
or are left floating (by options). Each bit of these output
latches can be set or cleared by the ²MOV [m], A²
(m=12H) instruction.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or to the accumulator. When a PA line is used as
an I/O line, the related PA line options should be config-
ured as NMOS with or without pull-high resistor. Once a
PA line is selected as a CMOS output, the I/O function
cannot be used.
The input state of a PA line is read from the related PA
pad. When the PA is configured as NMOS with or with-
out pull-high resistor, one should be careful when apply-
ing a read-modify-write instruction to PA. Since the
read-modify-write will read the entire port state (pads
state) firstly, execute the specified instruction and then
write the result to the port data register. When the read
operation is executed, a fault pad state (caused by the
load effect or floating state) may be read. Errors will then
occur.
There are three function pins that share with the PA port:
PA0/BZ, PA1/BZ and PA3/PFD.
The BZ and BZ are buzzer driving output pair and the
PFD is a programmable frequency divider output. If the
user wants to use the BZ/BZ or PFD function, the related
PA port should be set as a CMOS output. The buzzer
output signals are controlled by PA0 and PA1 data regis-
ters and defined in the following table.
PA1 Data PA0 Data
Register Register
PA0/PA1 Pad State
0
0
PA0=BZ, PA1=BZ
1
0
PA0=BZ, PA1=0
X
1
PA0=0, PA1=0
Note: ²X² stands for ²unused²
Rev. 1.10
18
September 25, 2002
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