HT82V24 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT82V24 Datasheet PDF : 21 Pages
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HT82V24
Functional Description
Integral Nonlinear (INL)
Integral nonlinear error refers to the deviation of each in-
dividual code from a line drawn from zero scale through
a positive full scale. The point used as zero scale occurs
1/2 LSB before the first code transition. A positive full
scale is defined as a level 1/2 LSB beyond the last code
transition. The deviation is measured from the middle of
each particular code to the true straight line.
Differential Nonlinear (DNL)
An ideal ADC exhibits code transitions that are exactly 1
LSB apart. DNL is the deviation from this ideal value.
Thus every code must have a finite width. No missing
codes guaranteed for the 16-bit resolution indicates that
all the 65536 codes respectively, are present in the
over-all operating range.
Offset Error
The first ADC code transition should occur at a level 1/2
LSB above the nominal zero scale voltage.
The offset error is the deviation of the actual first code
transition level from the ideal level.
Gain Error
The last code transition should occur for an analog
value of 1/2 LSB below the nominal full-scale voltage.
Gain error is the deviation of the actual difference be-
tween the first and the last code transitions and the ideal
difference between the first and the last code transi-
tions.
Sampling Delay
The sampling delay is the time delay that occurs when a
sampling edge is applied to the HT82V24 until the actual
sample of the input signal is held. Both CDSCLK1 and
CDSCLK2 sample the input signal during the transition
from high to low, so the sampling delay is measured
from each clock¢s falling edge to the instant the actual
internal sample is taken.
Internal Register Descriptions
Register
Name
Address
A2 A1 A0
Configuration 0
0
0
MUX
0
0
1
Red PGA
0
1
0
Green PGA 0
1
1
Blue PGA
1
0
0
Red Offset
1
0
1
Green Offset 1
1
0
Blue Offset
1
1
1
Data Bits
D8 D7 D6 D5 D4
D3
0
Don¢t care
3-CH CDS on
Clamp
Voltage
0
RGB/
BGR
Red
Green
Blue
0
0
0
0 MSB
0
0
0 MSB
0
0
0 MSB
MSB
MSB
MSB
Internal Register Map (ADI Mode)
D2 D1 D0
Enable
Power
Down
Input
Range
1 byte
out
0
0
0
LSB
LSB
LSB
LSB
LSB
LSB
Register
Name
Configuration
MUX
Red PGA
Green PGA
Blue PGA
Red Offset
Green Offset
Blue Offset
Address
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Data Bits
D8 D7 D6 D5 D4
D3
D2 D1 D0
1
Clamp Timing
Control
3-CH
CDS on
Clamp
Voltage
Enable
Power
Down
Input
Range
Output
Format
DEL
RGB/
BGR
Red
Green
Blue POSNNEG
VDEL
0
0
0 MSB
LSB
0
0
0 MSB
LSB
0
0
0 MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Internal Register Map (Wolfson Mode)
Rev. 1.00
5
September 7, 2005
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