HT82K94E(2005) 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT82K94E Datasheet PDF : 44 Pages
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HT82K94E/HT82K94A
Func. Name
CRC_ERR
EOT
NMI
R/W
Description
This bit is used to indicate there are CRCerror (bit=1). Firmware must do something to
R/W save the device and keep it in good condition.
This bit is set by SIE and cleared by F/W.
End of transaction flag, normal status is 1. If suspend=¢1¢ line & EOT=¢0¢ indicates that
R
something is wrong in the USB Interface. Firmware in-charge must do something to
save the device and keep it in good condition.
This bit is used to control whether the USB interrupt is output to the MCU in NAK re-
sponse to the PC Host IN or OUT token.
R/W
1: has only USB interrupt, data is transmitted to the PC host or data is received from
the PC Host
0: always has USB interrupt if the USB accesses FIFO0
Default 0
SIES Function
MISC register combines a command and status to control desired endpoint FIFO action and to show the status of the
desired endpoint FIFO. The MISC will be cleared by USB reset signal.
Bit No. Label R/W
Function
After setting the other status of the desired one in the MISC, endpoint FIFO can be
0
REQ R/W requested by setting this bit to ²1². After the job has been done, this bit has to be
cleared to ²0².
This bit defines the direction of data transferring between MCU and endpoint FIFO.
When the TX is set to ²1², this means that the MCU wants to write data to the end-
1
TX
R/W
point FIFO. After the job has been done, this bit has to be cleared to ²0² before termi-
nating request to represent the end of transferring. For reading action, this bit has to
be cleared to ²0² to represent that MCU wants to read data from the endpoint FIFO
and has to be set to ²1² after the job is done.
2
CLEAR R/W Clear the requested endpoint FIFO, even if the endpoint FIFO is not ready.
Defines which endpoint FIFO is selected, SELP1,SELP0:
4
3
SELP1
SELP0
00: endpoint FIFO0
R/W 01: endpoint FIFO1
10: endpoint FIFO2
11: endpoint FIFO3
Used to show that the data in endpoint FIFO is a SETUP command. This bit has to
5
SCMD R/W be cleared by firmware. That is to say, even the MCU is busy, the device will not miss
any SETUP commands from the host.
6
READY
R
Read only status bit, this bit is used to indicate that the desired endpoint FIFO is
ready to work.
7
LEN0
R/W
Used to indicate that a 0-sized packet is sent from a host to the MCU. This bit should
be cleared by firmware.
MISC (46H) Register
The MCU can communicate with the endpoint FIFO by setting the corresponding registers, of which address is listed in
the following table. After reading the current data, next data will show after 2ms, used to check the endpoint FIFO status
and response to MISC register, if read/write action is still going on.
Registers
R/W
Bank
Address
Bit7~Bit0
FIFO0
R/W
1
48H
Data7~Data0
FIFO1
R/W
1
49H
Data7~Data0
FIFO2
R/W
1
4AH
Data7~Data0
FIFO3
R/W
1
4BH
Data7~Data0
Rev. 1.00
20
November 22, 2005
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