HT82K94E_07 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT82K94E_07 Datasheet PDF : 43 Pages
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HT82K94E/HT82K94A
(TMR0/TMR1) pin. The timer mode functions as a nor-
mal timer with the clock source coming from the fSYS/4
(Timer0/Timer1). The pulse width measurement mode
can be used to count the high or low level duration of the
external signal (TMR0/TMR1). The counting is based on
the fSYS/4 (Timer0/Timer1).
In the event count or timer mode, once the Timer/Event
Counter 0/1 starts counting, it will count from the current
contents in the Timer/Event Counter 0/1 to FFH or
FFFFH. Once overflow occurs, the counter is reloaded
from the Timer/Event Counter 0/1 preload register and
generates the interrupt request flag (T0F/T1F; bit 5/6 of
INTC) at the same time.
In the pulse width measurement mode with the TON
and TE bits equal to one, once the TMR0/TMR1 has re-
ceived a transient from low to high (or high to low if the
TE bits is ²0²) it will start counting until the TMR0/TMR1
returns to the original level and resets the TON. The
measured result will remain in the Timer/Event Counter
0/1 even if the activated transient occurs again. In other
words, only one cycle measurement can be done. Until
setting the TON, the cycle measurement will function
again as long as it receives further transient pulse. Note
that, in this operating mode, the Timer/Event Counter
0/1 starts counting not according to the logic level but
according to the transient edges. In the case of counter
overflows, the counter 0/1 is reloaded from the
Timer/Event Counter 0/1 preload register and issues the
interrupt request just like the other two modes. To en-
able the counting operation, the timer ON bit (TON; bit 4
of TMR0C/TMR1C) should be set to 1. In the pulse width
measurement mode, the TON will be cleared automati-
cally after the measurement cycle is completed. But in
the other two modes the TON can only be reset by in-
structions. The overflow of the Timer/Event Counter 0/1
is one of the wake-up sources. No matter what the oper-
ation mode is, writing a 0 to ET0I/ET1I can disable the
corresponding interrupt services.
D a ta B u s
C o n tr o l B it P u ll- h ig h
DQ
In the case of Timer/Event Counter 0/1 OFF condition,
writing data to the Timer/Event Counter 0/1 preload regis-
ter will also reload that data to the Timer/Event Counter
0/1. But if the Timer/Event Counter 0/1 is turned on, data
written to it will only be kept in the Timer/Event Counter
0/1 preload register. The Timer/Event Counter 0/1 will still
operate until overflow occurs (a Timer/Event Counter 0/1
reloading will occur at the same time). When the
Timer/Event Counter 0/1 (reading TMR0/TMR1) is read,
the clock will be blocked to avoid errors. As clock blocking
may results in a counting error, this must be taken into
consideration by the programmer.
Input/Output Ports
There are 40 bidirectional input/output lines in the
microcontroller, labeled from PA to PE, which are
mapped to the data memory of [12H], [14H], [16H],
[18H] and [1AH] respectively. All of these I/O ports can
be used for input and output operations. For input oper-
ation, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction ²MOV
A,[m]² (m=12H, 14H, 16H, 18H or 1AH). For output op-
eration, all the data is latched and remains unchanged
until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC, PEC) to control the input/output configura-
tion. With this control register, CMOS/NMOS/PMOS
output or Schmitt trigger input with or without pull-high
resistor structures can be reconfigured dynamically un-
der software control. To function as an input, the corre-
sponding latch of the control register must write a ²1².
The input source also depends on the control register. If
the control register bit is ²1², the input will read the pad
state. If the control register bit is ²0², the contents of the
latches will move to the internal bus. The latter is possi-
ble in the ²read-modify-write² instruction. For output
function, CMOS is the only except port A which can be
V DD
W r ite C o n tr o l R e g is te r
C h ip R e s e t
R e a d C o n tr o l R e g is te r
CK Q
S
D a ta B it
DQ
P A 0 ~ P A 6 , P D 4 /T M R 0
P B 0~P B 7
P C 0~P C 7
P D 0~P D 7
P E 0~P E 7
W r ite D a ta R e g is te r
P A O u tp u t
C o n fig u r a tio n
R e a d D a ta R e g is te r
W a k e -u p fo r a n y I/O P o rt
P A 7 /T M R 1
C KS Q
M P u ll- lo w
U
X
W a k e - u p O p tio n fo r a n y I/O P o r t
Input/Output Ports
Rev. 1.50
16
October 11, 2007
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