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HT82K96E 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT82K96E
Holtek
Holtek Semiconductor Holtek
HT82K96E Datasheet PDF : 44 Pages
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Suspend Wake-Up Remote Wake-Up
If there is no signal on USB bus is over 3ms, the
HT82K96E will go into suspend mode . The Suspend
line (bit 0 of USC) will be set to 1 and a USB interrupt is
triggered to indicate the HT82K96E should jump to sus-
pend state to meet the 500mA USB suspend current
spec.
In order to meet the 500mA suspend current, the firm-
ware should disable the USB clock by clear the
USBCKEN (bit3 of the SCC) to ²0². The suspend cur-
rent is about 400mA.
Also the user can further decrease the suspend current
to 250mA by set the SUSP2 (bit4 of the SCC). But if the
SUSP2 is set, the user make sure cannot enable the
LVR OPT option, otherwise the HT82K96E will be reset.
When the resume signal is sent out by the host, the
HT82K96E will wake up the MCU by USB interrupt and
the Resume line (bit 3 of USC) is set. In order to make
HT82K96E work properly, the firmware must set the
USBCKEN (bit 3 of SCC) to 1 and clear the SUSP2 (bit4
of the SCC). Since the Resume signal will be cleared
before the Idle signal is sent out by the host and the Sus-
pend line (bit 0 of USC) is going to ²0². So when the
MCU is detecting the Suspend line (bit0 of USC), the
Resume line should be remembered and taken into con-
sideration.
After finishing the resume signal, the suspend line will
go inactive and a USB interrupt is triggered. The follow-
ing is the timing diagram
SUSPEND
U S B R e s u m e S ig n a l
U S B _ IN T
The device with remote wake up function can wake-up
the USB Host by sending a wake-up pulse through
RMWK (bit 1 of USC). Once the USB Host receive the
wake-up signal from HT82K96E. it will send a Resume
signal to device. The timing as follow:
SUSPEND
RM W K
M in . 1 U S B C L K
M in .2 .5 m s
U S B R e s u m e S ig n a l
U S B _ IN T
HT82K96E
To Configure the HT82K96E as PS2 Device
The HT82K96E can be define as USB interface or PS2
interface by configuring the SPS2 (bit 4 of USR) and
SUSB (bit 5 of USR). If SPS2=1, and SUSB=0, the
HT82K96E is defined as PS2 interface, pin USBD- is
now defined as PS2 Data pin and USBD+ is now de-
fined as PS2 Clk pin. The user can easy to read or write
the PS2 Data or PS2 Clk pin by accessing the corre-
sponding bit PS2DAI (bit 4 of USC), PS2CKI (bit 5 of
USC), PS2DAO (bit 6 of USC) and S2CKO (bit 7 of
USC) respectively.
The user should make sure that in order to read the data
properly, the corresponding output bit must set to 1. For
example, if it want to read PS2 Data by reading PS2DAI,
the PS2DAO should set to 1. Otherwise it always read 0.
If SPS2=0, and SUSB=1, the HT82K96E is defined as
USB interface. Both the USBD- and USBD+ is driving by
SIE of the HT82K96E. The user only write or read the
USB data through the corresponding FIFO.
Both SPS2 and SUSB is default ²0².
To Configure the ADC Block
The HT82K96E has built-in a 8-bit A/D converter with 6
channels (PB0~PB5). In order to make the A/D con-
verter more flexibility, there are two mode: External Ref-
erence voltage and Internal Reference voltage. It can
easy to configure by setting the ADREF (bit 6 of USR).
For External Reference voltage, the reference voltage
of the A/D converter comes from external PB6/VRL and
PB7/VRH pins. Otherwise, the reference voltage is
coming from the VDD and VSS of MCU.
PB0~PB5 is the 6-channels input of the A/D converter, it
can easy to define which channel is converting by con-
figuring ACS2~ACS0 (bit 2~0 of ADSC). Also there are
four converter clock source to be selected by setting
ADCS1 (bit 4 of ADSC), ADCS0 ( bit 3 of ADSC).
Once the ADON (bit 6 of ADSC) is set and send the start
pulse through START (bit 5 of ADSC). The A/D con-
verter will be in operation. There are EOCB (bit 7 of
ADSC) to indicate whether the A/D converter is busy or
not. The EOCB is clear when the conversion is com-
pleted. The user can read the converter data by reading
the register ADR. In order to meet 500uA suspend cur-
rent spec. . The user should disable the A/D by clearing
ADON before jump to suspend mode.
Rev. 2.00
19
October 11, 2007

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