IC42S16100 데이터 시트보기 (PDF) - Integrated Circuit Solution Inc

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IC42S16100

512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

Integrated Circuit Solution Inc 

IC42S16100

TWO BANKS OPERATION COMMAND TRUTH TABLE(1,2)

Operation

CS RAS CAS WE A11 A10 A9-A0

Previous State

Next State

BANK 0 BANK 1 BANK 0 BANK 1

DESL

NOP

BST

READ/READA

HXXXXXX

L HHHX X X

L HH L XXX

L H L H H H CA(3)

H H CA(3)

H L CA(3)

H L CA(3)

L H CA(3)

L H CA(3)

L L CA(3)

L L CA(3)

Any

Any

R/W/A

I

I/A

I/A

I/A

R/W

I/A

R/W

R/W/A

A

R/W/A

A

Any

Any

I/A

I/A

R/W/A

I

R/W/A

A

R/W/A

A

I/A

R/W

I/A

R/W

Any Any

Any Any

A

I/A

I

I/A

I/A

A

I/A

I

I/A

RP

A

RP

I/A

R

A

R

RP

I/A

RP

A

R

I/A

R

A

WRIT/WRITA

L H L L H H CA(3)

H H CA(3)

H L CA(3)

H L CA(3)

L H CA(3)

L H CA(3)

L L CA(3)

L L CA(3)

I/A

R/W

I/A

R/W

R/W/A

A

R/W/A

A

R/W/A

A

R/W/A

A

I/A

R/W

I/A

R/W

I/A

WP

A

WP

I/A

W

A

W

WP

I/A

WP

A

W

I/A

W

A

ACT

PRE/PALL

REF

MRS

L L H H H RA RA

L RA RA

L LHLXHX

XHX

HLX

HLX

LLX

LLX

L L LHXXX

LLLL

OPCODE

Any

I

I

Any

R/W/A/I I/A

I/A R/W/A/I

I/A R/W/A/I

R/W/A/I I/A

R/W/A/I I/A

I/A R/W/A/I

I

I

I

I

Any

A

A

Any

I

I

I

I

I/A

I

R/W/A/I I

I

I/A

I R/W/A/I

I

I

I

I

Notes:

1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column

Address

2. The device state symbols are interpreted as follows:

I

Idle (inactive state)

A

Row Active State

R Read

W Write

RP Read With Auto-Precharge

WP Write With Auto-Precharge

Any Any State

3. CA: A8,A9 = don't care.

18

Integrated Circuit Solution Inc.

DR024-0D 06/25/2004

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